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    SSTL IO Search Results

    SSTL IO Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    DCL541A01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: Low / Input disable Visit Toshiba Electronic Devices & Storage Corporation
    DCL542H01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=2:2) / Default Output Logic: High / Output enable Visit Toshiba Electronic Devices & Storage Corporation
    DCL541B01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: High / Input disable Visit Toshiba Electronic Devices & Storage Corporation
    DCL542L01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=2:2) / Default Output Logic: Low / Output enable Visit Toshiba Electronic Devices & Storage Corporation
    DCL540H01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=4:0) / Default Output Logic: High / Output enable Visit Toshiba Electronic Devices & Storage Corporation

    SSTL IO Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    G2992F1U

    Abstract: circuit diagram of ddr ram G2992 2N7002 SSTL-18 v5856 jedec MS-012-AA
    Text: G2992 Global Mixed-mode Technology Inc. 3A DDR Bus Termination Regulator Features General Description „ The G2992 is a linear regulator designed to meet the JEDEC SSTL-18, SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of


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    G2992 G2992 SSTL-18, 41TYP 016TYP 27TYP 05TYP G2992F1U circuit diagram of ddr ram 2N7002 SSTL-18 v5856 jedec MS-012-AA PDF

    Untitled

    Abstract: No abstract text available
    Text: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description „ The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational


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    G2996 G2996 SSTL-18 PDF

    power filter 25v

    Abstract: G2996 G2996F1UF G2996F1U G2996P1U SSTL-18
    Text: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description „ The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational


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    G2996 G2996 SSTL-18 power filter 25v G2996F1UF G2996F1U G2996P1U SSTL-18 PDF

    Untitled

    Abstract: No abstract text available
    Text: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description „ The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational


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    G2996 G2996 SSTL-18 PDF

    Untitled

    Abstract: No abstract text available
    Text: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description „ The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational


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    G2996 G2996 SSTL-18 PDF

    Untitled

    Abstract: No abstract text available
    Text: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.


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    UR5595 UR5595 QW-R502-062 PDF

    LP2995M

    Abstract: c151c LP2995 LP2995LQ LP2995LQX LP2995MR LP2995MRX LP2995MX M08A
    Text: General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The


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    LP2995 exte151° LLP-16 100pF LP2995 16-Lead LQA16A LP2995M c151c LP2995LQ LP2995LQX LP2995MR LP2995MRX LP2995MX M08A PDF

    Untitled

    Abstract: No abstract text available
    Text: CM3202-02 DDR VDDQ and VTT Termination Voltage Regulator Product Description The CM3202−02 is a dual−output low noise linear regulator designed to meet SSTL−2 and SSTL−3 specifications for DDR−SDRAM VDDQ supply and termination voltage VTT supply.


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    CM3202-02 CM3202â PDF

    LP2995

    Abstract: LP2995LQ LP2995LQX LP2995M LP2995MR LP2995MRX LP2995MX M08A
    Text: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The


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    LP2995 LP2995 LP2995LQ LP2995LQX LP2995M LP2995MR LP2995MRX LP2995MX M08A PDF

    northbridge

    Abstract: LP2995 LP2995LQ LP2995LQX LP2995M LP2995MX M08A
    Text: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients.


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    LP2995 LP2995 northbridge LP2995LQ LP2995LQX LP2995M LP2995MX M08A PDF

    Untitled

    Abstract: No abstract text available
    Text: LP2998 LP2998 DDR-I and DDR-II Termination Regulator Literature Number: SNVS521G LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of


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    LP2998 LP2998 SNVS521G SSTL-18 PDF

    Untitled

    Abstract: No abstract text available
    Text: IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 14-BIT REGISTERED BUFFER WITH SSTL I/O IDT74SSTVF16857 FEATURES: DESCRIPTION: • • • • • • • • The SSTVF16857 is a 14-bit registered buffer designed for 2.3V-2.7V


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    IDT74SSTVF16857 14-BIT IDT74SSTVF16857 100mA MIL-STD-883, 200pF, SSTVF16857 310mV PDF

    SSTV16857

    Abstract: No abstract text available
    Text: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 PRELIMINARY 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs


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    IDT74SSTV16857 14-BIT 100mA MIL-STD-883, 200pF, SSTV16857 310mV PDF

    LP2994

    Abstract: LP2994M LP2994MX M08A
    Text: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier


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    LP2994 LP2994 CSP-9-111S2) CSP-9-111S2. LP2994M LP2994MX M08A PDF

    Untitled

    Abstract: No abstract text available
    Text: CM3202-02 DDR VDDQ and VTT Termination Voltage Regulator Product Description The CM3202−02 is a dual−output low noise linear regulator designed to meet SSTL−2 and SSTL−3 specifications for DDR−SDRAM VDDQ supply and termination voltage VTT supply.


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    CM3202-02 CM3202-02/D PDF

    LP2995M

    Abstract: LP2995MRX LP2995MX M08A LP2995 LP2995LQ LP2995LQX LP2995MR PSOP8
    Text: General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The


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    LP2995 CSP-9-111C2) CSP-9-111S2) LP2995M LP2995MRX LP2995MX M08A LP2995LQ LP2995LQX LP2995MR PSOP8 PDF

    LP2994

    Abstract: LP2994M LP2994MX M08A
    Text: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier


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    LP2994 LP2994 LP2994M LP2994MX M08A PDF

    CSPT857C

    Abstract: IDT74SSTVF16857 SSTVF16857
    Text: IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: IDT74SSTVF16857 DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class I style data inputs/outputs


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    IDT74SSTVF16857 14-BIT 100mA MIL-STD-883, 200pF, SSTVF16857 310mV CSPT857C IDT74SSTVF16857 PDF

    SSTV16857

    Abstract: IDT74SSTV16857
    Text: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs


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    IDT74SSTV16857 14-BIT 100mA MIL-STD-883, 200pF, SSTV16857 310mV IDT74SSTV16857 PDF

    Untitled

    Abstract: No abstract text available
    Text: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 PRELIMINARY 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs


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    IDT74SSTV16857 14-BIT 100mA MIL-STD-883, 200pF, SSTV16857 310mV PDF

    Untitled

    Abstract: No abstract text available
    Text: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 PRELIMINARY 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs


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    IDT74SSTV16857 14-BIT 100mA MIL-STD-883, 200pF, SSTV16857 310mV PDF

    psop-8

    Abstract: 8 lead psop-8 NS package num. mra08a resistor 0,15 Ohm 5W DATA SHEET psop 44 northbridge Op amp circuit applications SSTL-2 5041c free circuit diagram of motherboard SO-8
    Text: LP2995 DDR Termination Regulator General Description Features The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The


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    LP2995 LP2995 CSP-9-111C2) CSP-9-111S2) CSP-9-111S2. psop-8 8 lead psop-8 NS package num. mra08a resistor 0,15 Ohm 5W DATA SHEET psop 44 northbridge Op amp circuit applications SSTL-2 5041c free circuit diagram of motherboard SO-8 PDF

    UR5595L

    Abstract: UR5595L-SH2-R UR5595 UR5595-S08-R UR5595-SH2-R
    Text: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR „ DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.


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    UR5595 UR5595 QW-R502-062 UR5595L UR5595L-SH2-R UR5595-S08-R UR5595-SH2-R PDF

    Untitled

    Abstract: No abstract text available
    Text: {¡J PERICOM PI3B3863 . 3.3V, 10-Bit, 2-Port BusSwitch with SSTL-2 Enable


    OCR Scan
    24-pin PI3B3863 10-Bit, PI3B3863 PS8167B PDF