LFXP2-17E-5QN208C
Abstract: lfxp2-5e-5ftn256c lfxp2-5e-5tn144c LFXP2-8E-5FTN256I 16X4 XP2-17 LFXP2-40E LFXP2-5E-6TN144C sequential gearbox LFXP2-8E-5TN144I
Text: LatticeXP2 Family Data Sheet DS1009 Version 01.7, April 2011 LatticeXP2 Family Data Sheet Introduction February 2008 Data Sheet DS1009 Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II
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DS1009
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HSTL15
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128eristics
XP2-17
LFXP2-17E-5QN208C
lfxp2-5e-5ftn256c
lfxp2-5e-5tn144c
LFXP2-8E-5FTN256I
16X4
XP2-17
LFXP2-40E
LFXP2-5E-6TN144C
sequential gearbox
LFXP2-8E-5TN144I
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LFXP2-17E-5QN208C
Abstract: FTN256 lfxp2-5e LFXP2-5E-5QN208C LFXP2-8E-6FTN256C lfxp2-8E LFXP2-30E-6FTN256C XP2 LFXP2-5E-5QN208C LFXP2-30E-5FTN256I LFXP2-5E-5FTN256C
Text: LatticeXP2 Family Data Sheet DS1009 Version 01.6, August 2008 LatticeXP2 Family Data Sheet Introduction February 2008 Data Sheet DS1009 • Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II
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DS1009
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HSTL15
HSTL18
XP2-17
LFXP2-17E-5QN208C
FTN256
lfxp2-5e
LFXP2-5E-5QN208C
LFXP2-8E-6FTN256C
lfxp2-8E
LFXP2-30E-6FTN256C
XP2 LFXP2-5E-5QN208C
LFXP2-30E-5FTN256I
LFXP2-5E-5FTN256C
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Untitled
Abstract: No abstract text available
Text: LatticeXP2 Family Data Sheet DS1009 Version 02.0, March 2014 LatticeXP2 Family Data Sheet Introduction February 2012 Data Sheet DS1009 Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II
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Untitled
Abstract: No abstract text available
Text: LatticeXP2 Family Data Sheet DS1009 Version 01.9, June 2013 LatticeXP2 Family Data Sheet Introduction February 2012 Data Sheet DS1009 Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II
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DS1009
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FTN256
Abstract: LFXP2-30E-5FTN256I LFXP2-8E-6FTN256C LFXP2-17E-5FTN256I LFXP2-8E-5FTN256C FTBGA 256 LFXP2-17E-6FT256I8W LFXP2-17E-7FTN256C LFXP2-5E-6TN144C LFXP2-5E-7FTN256C
Text: LatticeXP2 Family Data Sheet DS1009 Version 01.4, April 2008 LatticeXP2 Family Data Sheet Introduction February 2008 Preliminary Data Sheet DS1009 • Flexible I/O Buffer Features • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II
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DS1009
DS1009
HSTL15
HSTL18
FTN256
LFXP2-30E-5FTN256I
LFXP2-8E-6FTN256C
LFXP2-17E-5FTN256I
LFXP2-8E-5FTN256C
FTBGA 256
LFXP2-17E-6FT256I8W
LFXP2-17E-7FTN256C
LFXP2-5E-6TN144C
LFXP2-5E-7FTN256C
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GTLP16612
Abstract: SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH1645 SN74GTLPH16612 SSTL-3 sstl lvttl Translator
Text: White Paper Using MAX 7000B Devices to Replace I/O Drivers Introduction The Altera® MAX® 7000B device is the only product-term device capable of supporting the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM memory interfaces.
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GTLP16612
SN74GTLP1394
SN74GTLPH1612
SN74GTLPH1616
SN74GTLPH1645
SN74GTLPH16612
SSTL-3
sstl lvttl Translator
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vhdl code for ddr3
Abstract: point-to-point mini-lvds LVCMOS15 LVCMOS25 LVCMOS33 PCI33 mini-lvds source driver SSTL15D mini-lvds driver LVCMOS18
Text: LatticeECP3 sysIO Usage Guide June 2010 Technical Note TN1177 Introduction The LatticeECP3 sysIO™ buffers give the designer the ability to easily interface with other devices using advanced system I/O standards. This technical note describes the sysIO standards available and how to implement them using Lattice’s ispLEVER design software.
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TN1177
vhdl code for ddr3
point-to-point mini-lvds
LVCMOS15
LVCMOS25
LVCMOS33
PCI33
mini-lvds source driver
SSTL15D
mini-lvds driver
LVCMOS18
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74HC230
Abstract: HC210 BGA-614 EP2S180 EP2S30 EP2S60 EP2S90 HC220 HC230 HC240
Text: 8. Migrating Stratix II Device Resources to HardCopy II Devices H51024-1.4 Introduction Altera HardCopy® II devices and Stratix® II devices are both manufactured on a 1.2-V, 90-nm process technology and offer many similar features. Designers can use the Quartus® II software to migrate
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H51024-1
90-nm
74HC230
HC210
BGA-614
EP2S180
EP2S30
EP2S60
EP2S90
HC220
HC230
HC240
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EP2S90
Abstract: HC210 Stratix II EP2S60 HC220 HC230 HC240 EP2S180 EP2S30 EP2S60
Text: 8. Migrating Stratix II Device Resources to HardCopy II Devices H51024-1.3 Introduction Altera HardCopy® II devices and Stratix® II devices are both manufactured on a 1.2-V, 90-nm process technology and offer many similar features. Designers can use the Quartus® II software to migrate
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H51024-1
90-nm
EP2S90
HC210
Stratix II EP2S60
HC220
HC230
HC240
EP2S180
EP2S30
EP2S60
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TLK3114SA
Abstract: No abstract text available
Text: DLKPC192S 10ĆGbps ETHERNET LAN PHYSICAL CODING SUBLAYER PCS WITH SSTL XGMII INTERFACE SLLS536 – AUGUST 2002 D 10-Gbps Ethernet LAN PCS With 64b/66b D D ENDEC 10-Gbps Media-Independent Interface (XGMII) Using 2.5-V SSTL Class 2 Technology 10-Gbps 16-Bit Interface (XSBI) Using LVDS
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DLKPC192S
10Gbps
SLLS536
10-Gbps
64b/66b
16-Bit
289-Ball
TLK3114SA
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GTLP16612
Abstract: GTLP16T1655 SN74GTLP1394 SN74GTLPH1612 SN74GTLPH1616 SN74GTLPH16612
Text: Using MAX 7000B Devices to Replace I/O Drivers December 2002, ver. 1.0 Introduction Application Note 293 The Altera MAX® 7000B device is the only product-term device capable of supporting the GTL+, SSTL-2, and SSTL-3 standards used in processor interfaces, backplane drivers, and SDRAM memory interfaces.
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GTLP16612
GTLP16T1655
SN74GTLP1394
SN74GTLPH1612
SN74GTLPH1616
SN74GTLPH16612
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interfacing differential logic families 1998
Abstract: 15-V SSTL-18 HSTL standards
Text: Section IV. I/O Standards This section provides information on Stratix II GX single-ended, voltage-referenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 10, Selectable I/O Standards in Stratix II & Stratix II GX
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TLK3114SA
Abstract: No abstract text available
Text: DLKPC192S 10ĆGbps ETHERNET LAN PHYSICAL CODING SUBLAYER PCS WITH SSTL XGMII INTERFACE SLLS536 − AUGUST 2002 D 10-Gbps Ethernet LAN PCS With 64b/66b D D ENDEC 10-Gbps Media-Independent Interface (XGMII) Using 2.5-V SSTL Class 2 Technology 10-Gbps 16-Bit Interface (XSBI) Using LVDS
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DLKPC192S
10Gbps
SLLS536
10-Gbps
64b/66b
16-Bit
289-Ball
TLK3114SA
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ttl to mini-lvds
Abstract: EP2C5 mini lvds CII51010-2 EP2C20 EP2C35 EP2C50 SSTL-18 SSTL IO pad
Text: Section IV. I/O Standards This section provides information on Cyclone II single-ended, voltage referenced, and differential I/O standards. This section includes the following chapters: Revision History Altera Corporation • Chapter 10, Selectable I/O Standards in Cyclone II Devices
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PLL 4046 4011 4017
Abstract: phase angle controller SIII52001-1 SSTL-15 SSTL-18
Text: Stratix III Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com SIII5V2-1.3 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
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DDR2 sstl_18 class
Abstract: HSTL standards 15-V SSTL-18 N098
Text: Section III. I/O Standards This section provides information on Stratix II single-ended, voltagereferenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 4, Selectable I/O Standards in Stratix II and Stratix II GX
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HSTL standards
Abstract: 15-V SSTL-18
Text: Section IV. I/O Standards This section provides information on Stratix II GX single-ended, voltage-referenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 10, Selectable I/O Standards in Stratix II and Stratix II GX
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LVCMOS15
Abstract: LVCMOS25 LVCMOS33 PCI33 SSTL18II
Text: LatticeXP2 sysIO Usage Guide June 2010 Technical Note TN1136 Introduction The LatticeXP2 sysIO™ buffers give the designer the ability to easily interface with other devices using advanced system I/O standards. This technical note describes the sysIO standards available and how they can be implemented using Lattice’s ispLEVER design software.
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LVCMOS15
LVCMOS25
LVCMOS33
PCI33
SSTL18II
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SSTL "on-chip termination" 1998
Abstract: 15-V SSTL-18 DDR2 SDRAM sstl_18 HSTL standards
Text: Section III. I/O Standards This section provides information on Stratix II single-ended, voltagereferenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 4, Selectable I/O Standards in Stratix II & Stratix II GX
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SSTL-15
Abstract: mini-lvds EIA-644 SSTL-18 EP3SL70
Text: 7. Stratix III Device I/O Features SIII51007-1.9 Stratix III I/Os are specifically designed for ease of use and rapid system integration while simultaneously providing the high bandwidth required to maximize internal logic capabilities and produce system-level performance. Independent modular I/O
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SSTL-15
mini-lvds
EIA-644
SSTL-18
EP3SL70
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PLL 4046 4011 4017
Abstract: 5252 F 1107 SSTL-15 SIII52001-1 SSTL-18 4046 PLL Designers Guide 0906NS DDR SDRAM Controller VCO 1430 2230 MHz
Text: 1. Stratix III Device Datasheet: DC and Switching Characteristics SIII52001-1.3 Electrical Characteristics Operating Conditions When Stratix III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible
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PLL 4046 4011 4017
5252 F 1107
SSTL-15
SSTL-18
4046 PLL Designers Guide
0906NS
DDR SDRAM Controller
VCO 1430 2230 MHz
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LVCMOS25
Abstract: LVCMOS15 LVCMOS33 LVCMOS18 ECP2M date sheet of ninth class
Text: LatticeECP2/M sysIO Usage Guide June 2010 Technical Note TN1102 Introduction The LatticeECP2 and LatticeECP2M™ sysIO™ buffers give the designer the ability to easily interface with other devices using advanced system I/O standards. This technical note describes the sysIO standards available and
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LVCMOS25
LVCMOS15
LVCMOS33
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ECP2M
date sheet of ninth class
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TLK3114SA
Abstract: No abstract text available
Text: DLKPC192S 10ĆGbps ETHERNET LAN PHYSICAL CODING SUBLAYER PCS WITH SSTL XGMII INTERFACE SLLS536 – AUGUST 2002 D 10-Gbps Ethernet LAN PCS With 64b/66b D D ENDEC 10-Gbps Media-Independent Interface (XGMII) Using 2.5-V SSTL Class 2 Technology 10-Gbps 16-Bit Interface (XSBI) Using LVDS
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DLKPC192S
10Gbps
SLLS536
10-Gbps
64b/66b
16-Bit
289-Ball
TLK3114SA
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mini-lvds source driver
Abstract: ttl to mini-lvds EP2C5 HSTL standards linear handbook mini lvds national semiconductor handbook CII51010-2 EP2C20 EP2C35
Text: Section IV. I/O Standards This section provides information on Cyclone II single-ended, voltage referenced, and differential I/O standards. This section includes the following chapters: Revision History Altera Corporation • Chapter 10, Selectable I/O Standards in Cyclone II Devices
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