Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    SSTL25 Search Results

    SF Impression Pixel

    SSTL25 Price and Stock

    Omega Engineering MNS2-9-IN-TS-ST-L25

    WIRELESS DUCT TEMPERATURE SENSOR
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey MNS2-9-IN-TS-ST-L25 Bulk 1
    • 1 $359.05
    • 10 $359.05
    • 100 $359.05
    • 1000 $359.05
    • 10000 $359.05
    Buy Now

    SSTL25 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: iPEM 2.4Gb SDRAM-DDR AS4DDR32M72PBG1 32Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit FEATURES BENEFITS DDR SDRAM Data Rate = 200, 250, 266, 333Mbps Package: • 208 Plastic Ball Grid Array PBGA , 16 x 23mm-1.0mm pitch 2.5V ±0.2V core power supply


    Original
    AS4DDR32M72PBG1 32Mx72 333Mbps 23mm-1 208-PBGA PDF

    lfxp2-40e

    Abstract: LVCMOS25 LD48 LFXP2-17E-5FTN256C HB1004 ispLEVER project Navigator route place LFXP2-5E-5QN IPUG35 LFXP2-8E
    Text: LatticeXP2 Family Handbook HB1004 Version 02.9, May 2011 LatticeXP2 Family Handbook Table of Contents May 2011 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1


    Original
    HB1004 TN1144 TN1220. TN1143 lfxp2-40e LVCMOS25 LD48 LFXP2-17E-5FTN256C ispLEVER project Navigator route place LFXP2-5E-5QN IPUG35 LFXP2-8E PDF

    LCMXO2-1200HC-4TG100C

    Abstract: LCMXO2-256HC-4TG100I LCMXO2-1200 tn1200 lcmxo2 LCMXO2-1200HC-4TG100 LCMXO2-2000 LCMXO2-7000 MachXO2-1200 LCMXO2-4000HC
    Text: MachXO2 Family Handbook HB1010 Version 01.0, November 2010 MachXO2 Family Handbook Table of Contents November 2010 Section I. MachXO2 Family Data Sheet Introduction Features . 1-1


    Original
    HB1010 LCMXO2-1200HC-4TG100C LCMXO2-256HC-4TG100I LCMXO2-1200 tn1200 lcmxo2 LCMXO2-1200HC-4TG100 LCMXO2-2000 LCMXO2-7000 MachXO2-1200 LCMXO2-4000HC PDF

    TPE11

    Abstract: TPT20 CON6A v2 tpr4 pr48b PT13B condor E5 Condor LVCMOS15 LVCMOS25
    Text: LatticeEC Standard Evaluation Board – Revision B User’s Guide April 2007 ebug10_01.4 Lattice Semiconductor LatticeEC Standard Evaluation Board – Revision B User’s Guide Introduction The LatticeEC Standard Evaluation Board provides a convenient platform to evaluate, test and debug user


    Original
    ebug10 120-pin) 32-bit PVG5H503A01 TPE11 TPT20 CON6A v2 tpr4 pr48b PT13B condor E5 Condor LVCMOS15 LVCMOS25 PDF

    LVCMOS25

    Abstract: LVCMOS15 LVCMOS33 LVCMOS18 ECP2M date sheet of ninth class
    Text: LatticeECP2/M sysIO Usage Guide June 2010 Technical Note TN1102 Introduction The LatticeECP2 and LatticeECP2M™ sysIO™ buffers give the designer the ability to easily interface with other devices using advanced system I/O standards. This technical note describes the sysIO standards available and


    Original
    TN1102 LVCMOS25 LVCMOS15 LVCMOS33 LVCMOS18 ECP2M date sheet of ninth class PDF

    TN1178

    Abstract: DDR3 DIMM footprint LVCMOS15 LVCMOS25 LVCMOS33 SSTL15D k2xsc
    Text: LatticeECP3 High-Speed I/O Interface June 2010 Technical Note TN1180 Introduction LatticeECP3 devices support high-speed I/O interfaces, including Double Data Rate DDR and Single Data Rate (SDR) interfaces, using the logic built into the Programmable I/O (PIO). SDR applications capture data on one


    Original
    TN1180 TN1178 DDR3 DIMM footprint LVCMOS15 LVCMOS25 LVCMOS33 SSTL15D k2xsc PDF

    OSC4/SM

    Abstract: MDLS-20265 OPTREX C-51505 MDLS-24265 short stop 12v p18 30a rs232 converter dmx Mosfet J49 LCM-S01602 lcm-s02402 Vishay SOT23 MARKING F5
    Text: LatticeXP2 Advanced Evaluation Board User’s Guide January 2009 Revision: EB30_01.3 LatticeXP2 Advanced Evaluation Board User’s Guide Lattice Semiconductor Introduction The LatticeXP2 Advanced Evaluation Board provides a convenient platform to evaluate, test and debug user


    Original
    LatticeXP2-17 24-6R8 OSC4/SM MDLS-20265 OPTREX C-51505 MDLS-24265 short stop 12v p18 30a rs232 converter dmx Mosfet J49 LCM-S01602 lcm-s02402 Vishay SOT23 MARKING F5 PDF

    CON6A

    Abstract: K4T51163QG-HCE60 pDS4102-DL2 LVCMOS33 LVCMOS15 LVCMOS25 PB50B TPE11 PL43A FPGA48
    Text: LatticeEC Standard Evaluation Board – Revision A User’s Guide April 2007 EB07_02.4 Lattice Semiconductor LatticeEC Standard Evaluation Board – Revision A User’s Guide Introduction The LatticeEC Standard Evaluation Board provides a convenient platform to evaluate, test and debug user


    Original
    120-pin) 32-bit PVG5H503A01 CON6A K4T51163QG-HCE60 pDS4102-DL2 LVCMOS33 LVCMOS15 LVCMOS25 PB50B TPE11 PL43A FPGA48 PDF

    MachXO2-1200

    Abstract: TN1203 TN1199 GDDR71 Lattice XO2 IDDRX71A ODDRX71A MACHXO2 1200 pinout file ddrx2
    Text: Implementing High-Speed Interfaces with MachXO2 Devices November 2010 Advance Technical Note TN1203 Introduction In response to the increasing need for higher data bandwidth, the industry has migrated from the traditional Single Data Rate SDR to the Double Data Rate (DDR) architecture. SDR uses either the rising edge or the falling edge


    Original
    TN1203 1-800-LATTICE MachXO2-1200 TN1203 TN1199 GDDR71 Lattice XO2 IDDRX71A ODDRX71A MACHXO2 1200 pinout file ddrx2 PDF

    LC4064ZE

    Abstract: BSDL Files infineon LFXP6C-3FN256I "x-ray machine" K4H560838E LC4064 LC4256ZE LFXP10C-3F256I LFxP3C-3TN144C PCI x1 express PCB dimensions artwork
    Text: LatticeXP Family Handbook HB1001 Version 03.4, September 2010 LatticeXP Family Handbook Table of Contents September 2010 Section I. LatticeXP Family Data Sheet Introduction Features . 1-1


    Original
    HB1001 TN1050 TN1049 TN1082 TN1074 LC4064ZE BSDL Files infineon LFXP6C-3FN256I "x-ray machine" K4H560838E LC4064 LC4256ZE LFXP10C-3F256I LFxP3C-3TN144C PCI x1 express PCB dimensions artwork PDF

    PC8640

    Abstract: openpic
    Text: PC8640 and PC8640D Power Architecture Integrated Processor Datasheet - Preliminary Specification Features • • • • • • • • • • • • • Dual-e600 Power Architecture Processor Cores PD Typically 21.7W at 1.25 GHz VDD = 1.05V Selectable MPX Bus up to 600 MHz (64 bits)


    Original
    PC8640 PC8640D Dual-e600 125Gbaud) 64-bit 0948C openpic PDF

    pci slot pinout

    Abstract: e2v GTX 120 PC8640
    Text: PC8640 and PC8640D Power Architecture Integrated Processor Datasheet Features • • • • • • • • • • • • • Dual-e600 Power Architecture Processor Cores PD Typically 21.7W at 1.25 GHz VDD = 1.05V Selectable MPX Bus up to 600 MHz (64 bits)


    Original
    PC8640 PC8640D Dual-e600 125Gbaud) 64-bit Chan49 0948E pci slot pinout e2v GTX 120 PDF

    syscon

    Abstract: LFEC1E-3T100C ips works 6CW3
    Text: LatticeECP/EC Family Data Sheet Version 01.3 LatticeECP/EC Family Data Sheet Introduction November 2004 Preliminary Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 41K LUT4s • 65 to 576 I/Os • Density migration supported


    Original
    36x36 18x18 DDR400 200MHz) TN1052) TN1057) TN1053) syscon LFEC1E-3T100C ips works 6CW3 PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 04.4, April 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL


    Original
    HSTL15 TN1050) TN1052) TN1082) PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 03.0, September 2005 LatticeXP Family Data Sheet Introduction July 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original
    HSTL15 TN1050) TN1052) TN1082) PDF

    pt45

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.2, June 2006 LatticeSC Family Data Sheet Introduction June 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original
    DS1004 DS1004 700MHz 600Mbps 125Gbps) 110mW VCC12. LFSC25 900-Ball pt45 PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeECP/EC Family Handbook HB1000 Version 03.7, September 2012 LatticeECP/EC Family Handbook Table of Contents September 2012 Section I. LatticeECP/EC Family Data Sheet Introduction Features . 1-1


    Original
    HB1000 TN1008 TN1010 TN1018 TN1071 TN1074 TN1078 PDF

    pin configuration of 7496 IC

    Abstract: TMS 3617 Transistor TT 2246 ttl to mini-lvds EP2C35F672 IC 4033 pin configuration EP2C20F256 CI 4017 combinational digital lock circuit projects EP2C8F256
    Text: Cyclone II Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CII5V1-3.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and


    Original
    PDF

    EP2C5Q208C8

    Abstract: EP2C5T144 EP2C35F672
    Text: Cyclone II Device Handbook, Volume 1 Preliminary Information 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com CII5V1-1.1 Copyright 2004 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and


    Original
    EP2C50F484C6 EP2C50 EP2C50F484C7 EP2C50F484C8 EP2C50F672C6 EP2C50F672C7 EP2C50F672C8 EP2C5Q208C8 EP2C5T144 EP2C35F672 PDF

    LFE3-17EA

    Abstract: LFE3-35EA-6FN484C DS1021 ECP3-35 ECP3-95 16x4-Bit convolution encoders LFE335EA6FN484C LFE3-35EA-8FN484C LFE3-95EA-6FN484C
    Text: LatticeECP3 Family Data Sheet DS1021 Version 01.9EA, July 2011 LatticeECP3 Family Data Sheet Introduction December 2010 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic • Source synchronous standards support


    Original
    DS1021 DS1021 8b10b, 10-bit LatticeECP3-17EA 256-ball LatticeECP-35EA 256ball LFE3-17EA LFE3-35EA-6FN484C ECP3-35 ECP3-95 16x4-Bit convolution encoders LFE335EA6FN484C LFE3-35EA-8FN484C LFE3-95EA-6FN484C PDF

    LVCMOS25

    Abstract: LVCMOS18 LVCMOS33 SSTL-33 HSTL15 LVDS25E isplever VHDL SSTL18D LVCMOS15 SSTL33
    Text: TN1102_01.6J Apr. 2008 LatticeECP2/M sysIO使用ガイド はじめに LatticeECP2 とLatticeECP2M™ のsysIOバッファは先進のシステムI/O規格を用いて容易に他のデバイス とインターフェイスする機能を設計者に与えます。このテクニカルノートは利用できるsysIO規格について


    Original
    TN1102 DQS1618PIO1 TN1105 SDSBLVDSLVPECLSSTLHSTL9-19-2LatticeECP2/M LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 PR29C; PR48B; LVCMOS25 LVCMOS18 LVCMOS33 SSTL-33 HSTL15 LVDS25E isplever VHDL SSTL18D LVCMOS15 SSTL33 PDF

    DS1009J

    Abstract: 16J3 TN1137 dsp-219 TN1141 LVCMOS25
    Text: Aug. 2012 LatticeXP2 データシート LatticeXP2 ファミリ・データシート DS1009J Version 01.8b, August 2012 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders.


    Original
    DS1009J 7k10k TN1139, TN1144 TN1220 csBGA144 16J3 TN1137 dsp-219 TN1141 LVCMOS25 PDF

    transistor D 2395

    Abstract: bt 1690
    Text: Cyclone II Device Handbook, Volume 1 Preliminary Information 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com CII5V1-2.2 Copyright 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and


    Original
    896-Pin transistor D 2395 bt 1690 PDF

    Untitled

    Abstract: No abstract text available
    Text: Cyclone II Device Handbook, Volume 1 Preliminary Information 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com CII5V1-2.1 Copyright 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and


    Original
    896-Pin PDF