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    TB67H451AFNG Toshiba Electronic Devices & Storage Corporation Brushed Motor Driver/1ch/Vout(V)=50/Iout(A)=3.5 Visit Toshiba Electronic Devices & Storage Corporation
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    ams OSRAM Group AS5145B Motorboard

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    STM MOTOR Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    STM-16

    Abstract: overhead processor OC48 XRT94L55
    Text: XRT94L55 Preliminary SONET/SDH OC-48/STM-16, 4XOC-12/STM-4, 16XOC-3/STM-1 FRAMER/CONCENTRATOR WITH INTEGRATED CDR’S REV. P1.0.0 GENERAL DESCRIPTION The XRT94L55 is a SONET/SDH OC-48/STM-16, 4xOC-12/STM-4, 16xOC-3/STM-1 Framer/Concentrator with integrated CDR's.


    Original     		PDF XRT94L55 OC-48/STM-16, 4XOC-12/STM-4, 16XOC-3/STM-1 XRT94L55 16xOC-3/STM-1 48x48 OC-12/OC-3 STM-16 overhead processor OC48

    TXC-07905

    Abstract: AU-AIS MSP SNCP BP-51H TXC-07905BRBG 421L BY274
    Text: OED622 Device Dual STM-4/STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07905 DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED622, is a dual STM-4/STM-1 SDH framer and overhead terminator, virtual


    Original     		PDF OED622 TXC-07905 TXC-07905-MB, TU-12 TXC-07905 AU-AIS MSP SNCP BP-51H TXC-07905BRBG 421L BY274

    TXC-04246

    Abstract: TXC-07905 TU12S TXC-07905-MC TXC-06951 txc-0424 OED622 OED155TM EtherMap-3 Pt VTXP-6
    Text: OED622 Device Dual STM-4/STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07905 PRODUCT INFORMATION DESCRIPTION: ™ The Optimized Edge Device, OED622, is a dual STM-4/STM-1 SDH framer and overhead terminator, virtual


    Original     		PDF OED622 TXC-07905 TXC-07905-MC, TU-12 VTXPTM-12) TXC-06951 STM-4/STS-12 TXC-07900 OED155TM) TXC-04246 TXC-07905 TU12S TXC-07905-MC txc-0424 OED155TM EtherMap-3 Pt VTXP-6

    TXC-07905-MB

    Abstract: TXC-07905 OED622 B016H BP85H MSP SNCP h-12-H cu3ah B007H
    Text: OED622 Device Dual STM-4/STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07905 PRODUCT PREVIEW DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED622, is a dual STM-4/STM-1 SDH framer and overhead terminator, virtual


    Original     		PDF OED622 TXC-07905 TXC-07905-MB, OED622TM TXC-07905-MB TXC-07905 B016H BP85H MSP SNCP h-12-H cu3ah B007H

    ANSI T1.105

    Abstract: XRT95L34 XRT95L34IV Bellcore-253
    Text: áç PRELIMINARY XRT95L34 OC-12/STM-4, QUAD OC-3/STM-1 POS/ATM FRAMER WITH INTEGRATED CDR’S MARCH 2002 GENERAL DESCRIPTION The XRT95L34 is an OC-12/STM-4, Quad OC-3/ STM-1 POS/ATM Framer with integrated CDR’s. ATM direct mapping and cell delineation are supported, so


    Original     		PDF XRT95L34 OC-12/STM-4, XRT95L34 95L34 XRT95L34IV ANSI T1.105 XRT95L34IV Bellcore-253

    CY7C9538

    Abstract: CYS25G0101DX cypress 1994 sram zero concatenated and OC-3 and STM-1 3C6V 1xVC4-16c T1X15
    Text: CONFIDENTIAL CY7C9538 OC-48/STM-16 Framer with Reconfigurable VC–POSIC2GVC-R Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Programmable frame tagging engine for packet preclassification enables such features as


    Original     		PDF CY7C9538 OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xSTS-3c, 4xSTS-12c, 2xSTS-24c, 1xOC-48c CY7C9538 CYS25G0101DX cypress 1994 sram zero concatenated and OC-3 and STM-1 3C6V 1xVC4-16c T1X15

    SDH 209

    Abstract: 1xVC4-16c CY7C9538 CYS25G0101DX VC45V
    Text: CONFIDENTIAL CY7C9538 OC-48/STM-16 Framer with Reconfigurable VC–POSIC2GVC-R Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Programmable frame tagging engine for packet preclassification enables such features as


    Original     		PDF CY7C9538 OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xSTS-3c, 4xSTS-12c, 2xSTS-24c, 1xOC-48c SDH 209 1xVC4-16c CY7C9538 CYS25G0101DX VC45V

    CY7C9537B

    Abstract: CYS25G0101DX T1X15
    Text: CONFIDENTIAL CY7C9537B OC-48/STM-16 Framer–POSIC2G Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated — Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] — Complies with Bellcore GR253 rev.1, 1997[3]


    Original     		PDF CY7C9537B OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xSTS-3c/VC4, 4xSTS-12c/VC4-4c, 2xSTS-24c/VC4-8c, 1xSTS-48c/VC4-16c CY7C9537B CYS25G0101DX T1X15

    nobl sram 1994

    Abstract: CY7C9536B-BLC CY7C9536B CYS25G0101DX VC45V
    Text: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997


    Original     		PDF CY7C9536B OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xOC-3 4xOC-12 OC-48 50-Mbps nobl sram 1994 CY7C9536B-BLC CY7C9536B CYS25G0101DX VC45V

    cmos aps

    Abstract: CYS25G0101DX OC48
    Text: PRELIMINARY CONFIDENTIAL CY7C9537 OC-48/STM-16 Framer - POSIC2G Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and nonconcatenated — Complies with ITU-Standards G.707/Y.1322 and G.783 — Complies with Bellcore GR253 rev.1, 1997


    Original     		PDF CY7C9537 OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xOC-3/STM-1 4xOC-12/STM-4 CYS25G0101DX OC-48 cmos aps CYS25G0101DX OC48

    ANSI T1.105

    Abstract: No abstract text available
    Text: áç PRELIMINARY XRT95L34 OC-12/STM-4, QUAD OC-3/STM-1 POS/ATM FRAMER WITH INTEGRATED CDR’S MARCH 2002 GENERAL DESCRIPTION The XRT95L34 is an OC-12/STM-4, Quad OC-3/ STM-1 POS/ATM Framer with integrated CDR’s. ATM direct mapping and cell delineation are supported, so


    Original     		PDF XRT95L34 OC-12/STM-4, XRT95L34 ANSI T1.105

    prbs parity checker and generator

    Abstract: RGPI5 4-bit even parity checker circuit diagram BY339 relay cross reference AC03 nec SDH 209 XRT95L34 XRT95L34IV b20 p03
    Text: áç PRELIMINARY XRT95L34 OC-12/STM-4, QUAD OC-3/STM-1 POS/ATM FRAMER WITH INTEGRATED CDR’S APRIL 2002 GENERAL DESCRIPTION The XRT95L34 is an OC-12/STM-4, Quad OC-3/ STM-1 POS/ATM Framer with integrated CDR’s. ATM direct mapping and cell delineation are supported, so


    Original     		PDF XRT95L34 OC-12/STM-4, XRT95L34 584-pin prbs parity checker and generator RGPI5 4-bit even parity checker circuit diagram BY339 relay cross reference AC03 nec SDH 209 XRT95L34IV b20 p03

    T1X15

    Abstract: CY7C9536B CYS25G0101DX OIF-SPI3-01 TRS-X
    Text: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997


    Original     		PDF CY7C9536B OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xOC-3 4xOC-12 OC-48 50-Mbps T1X15 CY7C9536B CYS25G0101DX OIF-SPI3-01 TRS-X

    4x2 mux

    Abstract: GR-253 PEB1756E STM-16 STS-48 to48c
    Text: Preliminary PEB1756E TETHYS 448 16 STS-48/STM-16 MUX/DEMUX REV. P1.0.0 GENERAL DESCRIPTION Tethys™ 448 is optimized for SONET/SDH applications as a full-duplex sixteen STS-48/STM-16 or a mix of sixteen STS-12/STM-4 and STS-3/STM-1 MUX/DEMUX with full framer functionality including


    Original     		PDF PEB1756E STS-48/STM-16 STS-12/STM-4 STS-48/ STM-16, PEB1756E STS-48 4x2 mux GR-253 STM-16 STS-48 to48c

    10UTOPIA

    Abstract: CY7C9537B CYS25G0101DX 6AE11
    Text: CONFIDENTIAL CY7C9537B OC-48/STM-16 Framer–POSIC2G Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated — Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] — Complies with Bellcore GR253 rev.1, 1997[3]


    Original     		PDF CY7C9537B OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xSTS-3c/VC4, 4xSTS-12c/VC4-4c, 2xSTS-24c/VC4-8c, 1xSTS-48c/VC4-16c 10UTOPIA CY7C9537B CYS25G0101DX 6AE11

    CY7C9536B-BLC

    Abstract: CY7C9536B CYS25G0101DX RXD13
    Text: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997


    Original     		PDF CY7C9536B OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xOC-3 4xOC-12 OC-48 50-Mbps CY7C9536B-BLC CY7C9536B CYS25G0101DX RXD13

    T1X15

    Abstract: CY7C9536B-BLC cfk logic chip CY7C9536B CYS25G0101DX
    Text: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997


    Original     		PDF CY7C9536B OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xOC-3 4xOC-12 OC-48 50-Mbps T1X15 CY7C9536B-BLC cfk logic chip CY7C9536B CYS25G0101DX

    PIR 203B

    Abstract: 4312 020 36643 lcd power board schematic hp 1502 lcd power board schematic APS 254 TCS 3414 MOTOROLA SOC 124A lcd power board schematic APS 252 ISO13239 h19 0549 9 ADM 3053
    Text: PHAST-12 Device Programmable, High-Performance ATM/Packet/Transmission SONET/SDH Terminator for Level 12 TXC-06112 DATA SHEET PRELIMINARY DESCRIPTION FEATURES • Integrated clock recovery and synthesis for four OC-3c/STM-1 signals or one OC-12/OC-12c/ STM-4/STM-4c signal


    Original     		PDF PHAST-12 TXC-06112 OC-12/OC-12c/ OC-12/STM-4 OC-48/STM-16 STS-12c/STM-4c TXC-06112-MB PIR 203B 4312 020 36643 lcd power board schematic hp 1502 lcd power board schematic APS 254 TCS 3414 MOTOROLA SOC 124A lcd power board schematic APS 252 ISO13239 h19 0549 9 ADM 3053

    AU-AIS

    Abstract: Digital Alarm Clock by using ttl LXT e2 LXT6251A marking cod A2 regenerator in optical D4D12 LXT6051 LXT6051QE SSI 7200
    Text: LXT6051 STM-1/0 SDH Overhead Terminator Datasheet The LXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0 51Mb/s and STM-1 (155Mb/s) multiplexers. It provides micro-controller access for performance monitoring,


    Original     		PDF LXT6051 LXT6051 51Mb/s) 155Mb/s) LXT6251A AU-AIS Digital Alarm Clock by using ttl LXT e2 LXT6251A marking cod A2 regenerator in optical D4D12 LXT6051QE SSI 7200

    2.5G DWDm

    Abstract: TO-48C 2.5G GR-253 PEB1756E STM-16 STS-48 to48c
    Text: PRELIMINARY PRODUCT FLYER Semiconductor Solutions for High Speed Communications and Fiber Optic Applications Tethys 448 is optimized for SONET/SDH applications as a full-duplex sixteen STS-48/STM-16 or a mix of sixteen STS-12/STM-4 and STS-3/STM-1 MUX/DEMUX with


    Original     		PDF STS-48/STM-16 STS-12/STM-4 STS-48/ STM-16, 2.5G DWDm TO-48C 2.5G GR-253 PEB1756E STM-16 STS-48 to48c

    Untitled

    Abstract: No abstract text available
    Text: EtherPHAST -48 Plus Device OC-48/STM-16 SONET/SDH Ethernet Mapper TXC-06742 DATA SHEET PRODUCT PREVIEW TXC-06742-MB, Ed. 4 December 2005 FEATURES APPLICATIONS • 1x STS-48/STM-16 or 4x STS-12/STM-4 framer with TOH processing, 4x 622 LVDS line side interface


    Original     		PDF OC-48/STM-16 TXC-06742 TXC-06742-MB, STS-48/STM-16 STS-12/STM-4 AU-4-16c/AU-4-4c/AU-4/AU-3/TU-3 OC-12/4x EtherPHAST-48

    D1 3009k

    Abstract: 6 pin 2D 1002 ring COUNTER
    Text: IBM3009K2672 IBM SONET/SDH Framer Features • Integrated clock recovery and synthesis for four OC-3c/STM-1 signals or one OC-12/OC-12c/ STM-4/STM-4c signal • OC-12/STM-4 or quad OC-3c/STM-1 framing and performance monitoring • Expansion port for OC-48/STM-16 operation


    OCR Scan     		PDF IBM3009K2672 OC-12/OC-12c/ OC-12/STM-4 OC-48/STM-16 STS-12c/STM-4c 3009K D1 3009k 6 pin 2D 1002 ring COUNTER

    Untitled

    Abstract: No abstract text available
    Text: Datasheet JUNE 1999 Revision 2.0 LXT6051 STM-170 SDH Overhead Terminator General Description The LXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0 51Mb/s and STM-1 (155Mb/s) multiplexers. It provides


    OCR Scan     		PDF LXT6051 STM-170 LXT6051 51Mb/s) 155Mb/s) LXT6251

    GG1Q

    Abstract: No abstract text available
    Text: DATASHEET PM PMC-970133 ISSUE2 PRELIMINARY 1 PMC-Sierra, Inc. PMS342 spbctra -155 SONET/SDH PA YLOAD EXTRACTOR/ALIGNER FEATURES • Monolithic SONET/SDH PAYLOAD EXTRACTOR/ALIGNER for use in STS-1 STM-0/AU3 , STS-3 (STM-1/AU3) or STS-3c (STM-1 /AU4) interface


    OCR Scan     		PDF PMC-970133 PMS342 20x20 GG1Q