SY100S360JC Search Results

SY100S360JC Datasheets (7)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
SY100S360JC		Micrel Semiconductor	Logic - Parity Generators and Checkers, Integrated Circuits (ICs), IC 8-BIT GEN/CHKER 28PLCC		Original	PDF
SY100S360JC		Micrel Semiconductor	DUAL PARITY CHECKER/ GENERATOR		Original	PDF
SY100S360JC		Microchip Technology	Integrated Circuits (ICs) - Logic - Parity Generators and Checkers - IC 8-BIT GEN/CHKER 28PLCC		Original	PDF
SY100S360JC		Synergy Semiconductor	DUAL PARITY CHECKER/GENERATOR		Scan	PDF
SY100S360JC		Synergy Semiconductor	DUAL PARITY CHECKER/GENERATOR		Scan	PDF
SY100S360JCTR		Micrel Semiconductor	DUAL PARITY CHECKER/ GENERATOR		Original	PDF
SY100S360JCTR		Synergy Semiconductor	DUAL PARITY CHECKER/GENERATOR		Scan	PDF

SY100S360JC Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
ZB500 Abstract: "Parity Checker" application of parity checker/generator F100K SY100S360 SY100S360FC SY100S360JC SY100S360JCTR Text: DUAL PARITY CHECKER/ GENERATOR FEATURES I1a I0a I2a I4a I3a VEES PIN CONFIGURATIONS I5a 11 10 9 8 7 6 5 I6a I7a VEE VEES I0b BLOCK DIAGRAM I0a I1a I2b Za Top View PLCC J28-1 Ia Za VCCA VCC VCC C Zb I6a I7a I5a I4b I5b I6b 2 3 17 16 I4a I3a 15 14 I2a I1a 13	Original	PDF	J28-1 F24-1 SY100S3 SY100S360JC SY100S360JCTR SY100S360 F24-1) ZB500 "Parity Checker" application of parity checker/generator F100K SY100S360 SY100S360FC SY100S360JC SY100S360JCTR
F100K Abstract: SY100S360 SY100S360FC SY100S360FCTR SY100S360JC SY100S360JCTR Marking ZB Text: Micrel, Inc. DUAL PARITY CHECKER/ GENERATOR FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S360 SY100S360 DESCRIPTION The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each	Original	PDF	SY100S360 SY100S360 M9999-032406 F100K SY100S360FC SY100S360FCTR SY100S360JC SY100S360JCTR Marking ZB
F100K Abstract: SY100S360 SY100S360FC SY100S360JC SY100S360JCTR Text: DUAL PARITY CHECKER/ GENERATOR FEATURES I1a I0a I2a I4a I3a VEES PIN CONFIGURATIONS I5a 11 10 9 8 7 6 5 I6a I7a VEE VEES I0b BLOCK DIAGRAM I0a I1a I2b Za Top View PLCC J28-1 Ia Za VCCA VCC VCC C Zb I6a I7a I5a I4b I5b I6b 2 3 17 16 I4a I3a 15 14 I2a I1a 13	Original	PDF	J28-1 F24-1 SY100S3F24-1 SY100S360JC SY100S360JCTR SY100S360 F24-1) F100K SY100S360 SY100S360FC SY100S360JC SY100S360JCTR
application of parity checker/generator Abstract: F100K SY100S360 SY100S360JC SY100S360JCTR Text: Micrel, Inc. DUAL PARITY CHECKER/ GENERATOR FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S360 SY100S360 DESCRIPTION The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each	Original	PDF	SY100S360 SY100S360 M9999-042307 application of parity checker/generator F100K SY100S360JC SY100S360JCTR
"Parity Checker" Abstract: F100K SY100S360 SY100S360DC SY100S360FC D0G22 ha13 Text: * DUAL PARITY CHECKER/GENERATOR SYNERGY S E M IC O N D U C T O R FEATURES SY100S360 DESCRIPTION • Max. propagation delay of 2200ps I e e min. of -70mA ■ ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option:	OCR Scan	PDF	SY100S360 2200ps of-70mA F100K SY100S360 T0013ai 000223b "Parity Checker" F100K SY100S360DC SY100S360FC D0G22 ha13
"Parity Checker" Abstract: F100K SY100S360 SY100S360DC SY100S360FC Text: « DUAL PARITY CHECKER/GENERATOR SYNERGY SEMICONDUCTOR FEATURES SY100S360 D E S C R IP T IO N • Max. propagation delay of 2200ps ■ I ee min. of -70mA ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option:	OCR Scan	PDF	SY100S36Â 2200ps -70mA F100K SY100S360 000CH2G sy100s360 SY100S360DC D24-1 SY100S360FC "Parity Checker" F100K
Untitled Abstract: No abstract text available Text: * SYNERGY SEMICONDUCTOR DUAL PARITY CHECKER/GENERATOR FEATURES SY100S360 DESCRIPTION The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each and the parity output is at a logic LOW when an even	OCR Scan	PDF	SY100S360 SY100S360 75Ki2
Untitled Abstract: No abstract text available Text: « DUAL PARITY CHECKER/GENERATOR SYNERGY SEMICONDUCTOR FEATURES SY100S360 DESCRIPTION • Max. propagation delay of 2200ps ■ Iee mln. of -70mA ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option: — VEE = -4.2V to -5.46V	OCR Scan	PDF	SY100S360 2200ps -70mA F100K SY100S360 SY100S360DC D24-1 SY100S360FC F24-1
Untitled Abstract: No abstract text available Text: * SYNERGY DUAL PARITY CH ECKER /G EN ERATO R SY100S360 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 2200ps Iee min. o f-70 m A Industry standard 100K ECL levels Extended supply voltage option: V ee = -4.2V to -5.5V Voltage and temperature compensation for	OCR Scan	PDF	SY100S360 2200ps SY100S360
Untitled Abstract: No abstract text available Text: * DUAL PARITY CHECKER/GENERATOR SYNERGY SY100S360 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 2200ps min. o f-7 0m A Industry standard 100K ECL levels Iee Extended supply voltage option: V ee = -4 .2V to -5.5V Voltage and temperature compensation for	OCR Scan	PDF	SY100S360 2200ps F100K 24-pin 28-pin SY100S360
Untitled Abstract: No abstract text available Text: * DUAL PARITY CHECKER/GENERATOR SYNERGY SEMICONDUCTOR FEATURES SY100S360 DESCRIPTION • Max. propagation delay of 2200ps ■ Iee min. of -70mA ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option: V ee = -4.2V to -5.5V	OCR Scan	PDF	SY100S360 2200ps -70mA SY100S360
1913B Abstract: No abstract text available Text: n i j a I. SYNERGY pa m i y HFf'KF'R/i’f NFjflMi ='''<»«60 3 E M ¡C O N D U C I O h D ES C R IPTIO N • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Max. propagation delay of 2200ps Iee min. of -70mA Industry standard 100K ECL levels Extended supply voltage option:	OCR Scan	PDF	2200ps -70mA F100K 24-pin 28-pin SY100S360DC SY100S360FC SY100S360JC SY10OS360JCTR 1913B