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    Abstract: No abstract text available
    Text: PRELIMINARY T709149S HIGH-SPEED 36K 4K x 9-BIT SYNCHRONOUS PIPELINED DUAL-PORT SRAM F e a tu re s ♦ 13ns cycle time, 76MHz operation in pipeline mode * Architecture based on Dual-Port SRAM cells - - Allow s fu ll sim ultaneous access from both ports


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    PDF IDT709149S 8/10/12ns T709149S 1500m 76MHz 492-M