Untitled
Abstract: No abstract text available
Text: Advance information •■ I l AS4LC2M8S0 AS4LC1M1ÓS0 A 3.3V 2 M x 8 /lM x 16 CMOS synchronous DRAM Features Automatic and direct precharge Burst read, single write Can assert random column address in every cycle LVl'l'L compatible V O 3.3Vpower supply JEDEC standard package, pinout and function
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44-pin
50-pin
44-pin
50-pin
AS4LC1M16S0-8TC
ASHX2M890-10TC
AStLClM1690-10TC
AS4LC2M8S0-12TC
AS4IC1M16S0-12TC
T90PII400
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Untitled
Abstract: No abstract text available
Text: AS7C4096 AS7C34096 A 5V/3.3V 512Kx8 CMOS SRAM Features • Organization: 262,144 words x 16 bits • High speed - 12/15/ 20/ 25 ns address access time - 5/ 5/ 617 ns output enable access time • Law power consumption - .Active: 990 mW max 20 ns cycle, 5V
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AS7C4096
AS7C34096
512Kx8
36-pin
44-pin
T90PII
AS7C34096-25TIâ
AS7C4096-25T1
34096-25T1
AS7C4096
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Untitled
Abstract: No abstract text available
Text: Enhanced IVfemoiy Systems be. DM512K32ST/DM512K36ST 512Kb x 32/512Kb x 36 EDRAM SIMM Product Specification Features A rchitecture • 4KByte SRAM Cache Memory for 12ns Random Reads Within Four s tiv e s Pages Multibank Cache ■ Fast DRAM Array for 30ns Access to Any New Page
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DM512K32ST/DM512K36ST
512Kb
32/512Kb
JEDEC512Kx
DM2203T-XX,
DM2213T-XX,
DM512K32ST)
R6-R10
100KS2
DM512K36ST-
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Untitled
Abstract: No abstract text available
Text: F n h fl n rp H DM2203/2213 Multibank EDOEDRAM 5 1 2 K b * 8 Product Specification H Features • 8Kbit SRAM Cache Memory for 12ns Random Reads Within Four Active Pages Mu iti bank Cache ■ Fast 4Mbit DRAM Array for 30ns Access to Any New Page ■ Write Posting Ftegister for 12ns Random Writes and Burst Writes
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DM2203/2213
256-byte
DM2203T-
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Untitled
Abstract: No abstract text available
Text: Enhanced DM1M64DTE/DM1M72DTE M ultibank Burst EDOEDRAM 1Mb x 64/1Mb x 72 Enhanced DRAM DIMM IVfemoiy Suterns be. H Product Specification Features row register over a 2Kbyte-wide bus in just 18ns for an effective cache • 16Kbytes SRAM Cache Memory for 12ns Random Reads Within
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DM1M64DTE/DM1M72DTE
64/1Mb
16Kbytes
168BD5-TR
DM1M72DTE-
72-bit
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Untitled
Abstract: No abstract text available
Text: Enhanced IVfemoiy Systems Inc. DM512K32ST6/DM512K36ST6 Multibank EDO 512Kb x 32/512Kb x 36 EDRAM SIMM Product Specification Features Architecture • 4KByte SRAM Cache Memory for 12ns Random Reads Within Four stive s Pages Multibank Cache ■ Fast DRAM Array for 30ns Access to Any New Page
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DM512K32ST6/DM512K36ST6
512Kb
32/512Kb
512K36ST6-
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U23C-36
Abstract: No abstract text available
Text: •K p n h o n p p f V i i DM 1M64DT6/DM1M72DT6 Multibank EDOEDRAM m m * d 1 2 ra m d i m m ProductSpecification Features ■ 16Kbytes SAM Cache Memory for 12ns Random Reads Within Eght Active Pages Multi bank CSche ■ Fast 8Mbyte DRAM Array for 30ns Access to Any New Page
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DM1M64DT6/DM1M72DT6
16Kbytes
DM1M72DT6-
72-bit
U23C-36
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Untitled
Abstract: No abstract text available
Text: •K Pnha nppH 16MBit Enhanced SDRAM Family M W « 1Mbx16 *7 1 Preliminary Features ■ Pin and Timing Compatible with I ndustry Standard SDRAM ■ Synchronous Clock Operation at Burst Rates Up to 166 MHz ■ Fast 30ns 16Mbit DRAM Organized in 2 Banks of 8Mbits
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16MBit
1Mbx16
133MHz
SM2404T1-7
16Mbit
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UAA 1006
Abstract: AS4LC1M16SO AS4LC1M16S0 1024x512x8 DTA 1006
Text: Advance informatio AS4LC 2M8S0 AS4LC1 M16S0 3.3V 2 M x 8 /lM x 1 6 CMOS synchronous DRAM Features A utom atic and direct precharge B urst read, single w rite Can assert ra n d o m co lu m n address in every cycle LVTTL co m patible V O 3 .3 Y p o w e r supply
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M16S0
t90pii
44-pin
AS4LC2M890-
AS4LC2M8S0-12TC
50-pin
AS4LC1M16S0-8TC
AS4LC1M16SQ-10TC
AS4IC1M16S0-12TC
6ID11-3O0Q0-Ã
UAA 1006
AS4LC1M16SO
AS4LC1M16S0
1024x512x8
DTA 1006
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Untitled
Abstract: No abstract text available
Text: Enhanced DM2223/2233 Multibank Burst EDOEDRAM 512Kb x 8 Enhanced Dynamic RAM I V f e m o iy S y s t e m s In c . Product Specification Features • 8Kbit SRAM Cache Memory for 12ns Random Reads Within Four Active Pages Multi bank Cache ■ Fast 4Mbit DRAM Array for 30ns Access to Any New Page
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DM2223/2233
512Kb
DM2223T-
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Untitled
Abstract: No abstract text available
Text: Advance information •■ I l AS4LC2M8S0 AS4LC1M1ÓS0 A 3.3V 2 M x 8 /lM x 16 CMOS synchronous DRAM Features Automatic and direct precharge Burst read, single write Can assert random column address in every cycle LVl'l'L compatible V O 3.3Vpower supply JEDEC standard package, pinout and function
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OCR Scan
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PDF
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44-pin
50-pin
50-pin
AS4LC1M16S0-8TC
ASHX2M890-10TC
AStLClM1690-10TC
AS4LC2M8S0-12TC
AS4IC1M16S0-12TC
T90PII400
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Untitled
Abstract: No abstract text available
Text: AS7C1026 AS7C31026 A 5V/3.3V 64Kx 16 CMOS SRAM Features • Organization: 262,144 words x 16 bits • High speed - 1 2 /1 5 / 20/ 25 ns address access time - 5/ 5/ 6 1 7 ns output enable access time • Law power consumption - .Active: 770 mW max 20 ns cycle, 5V
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AS7C1026
AS7C31026
144-pin
AS7C513)
AS7C3128K16)
AS7C4098)
cu26-20JC
AS7C1026-12TC
AS7C1026-15TC
AS7C1026-20TC
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Untitled
Abstract: No abstract text available
Text: Enhanced IVfemoiySuterns be. DM512K64DT6/DM512K72DT6 Multibank EDO EDRAM 512Kb x 64/512Kb x 12 Enhanced DRAM DIMM Product Specification Features • 8 Kbytes SRAM Cache Memory for 12ns Random Reads Within Four Active Pages Multi bank Cache ■ Fast 4Mbyte DRAM Array for 30ns Access to Any New Page
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DM512K64DT6/DM512K72DT6
64/512Kb
72-bit
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