TAP ME Search Results

TAP ME Result Highlights (5)

Part	Manufacturer	Description
X9401WV24IZ-2.7	Renesas Electronics Corporation	Quad, 64 Tap, Digitally Controlled Potentiometer (XDCP™)
X9401WS24IZ-2.7	Renesas Electronics Corporation	Quad, 64 Tap, Digitally Controlled Potentiometer (XDCP™)
X9401WS24IZ-2.7T1	Renesas Electronics Corporation	Quad, 64 Tap, Digitally Controlled Potentiometer (XDCP™)
X9401WV24IZ-2.7T1	Renesas Electronics Corporation	Quad, 64 Tap, Digitally Controlled Potentiometer (XDCP™)
ISL23418UFUZ	Renesas Electronics Corporation	Single, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

TAP ME Price and Stock

Filter by Manufacturer


KAGA FEI America Inc MB85RC64TAPN-G-AMEWE1 F-RAM 64kbit FRAM, I2C, 1.8V 3.6V - SON8 T&R
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Mouser Electronics	MB85RC64TAPN-G-AMEWE1		12,313			1 $1.7 10 $1.56 100 $1.35 1000 $1.27 10000 $1.17	Buy Now
Xeltek Inc Lens and Tape Attachment Frame Controller Accessories Automated Programmer Accessories
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Mouser Electronics	Lens and Tape Attachment Frame					1 $1350.98 10 $1350.98 100 $1350.98 1000 $1350.98 10000 $1350.98	Get Quote

TAP ME Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: 10K ECL Logic Buffered Delay 16-Pin Modules 5-Tap: DECL • Single: FECL • Triple: MECL Electrical Specifications at 25OC Tap Delay Tolerances +/- 5% or 1.5ns +/- 0.8ns <10ns 10K ECL 5 Tap P/N Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5 DECL-6 2.0 3.0 4.0 5.0	Original	16-Pin DECL-10 DECL-12 DECL-15 DECL-20 DECL-25 DECL-30 DECL-35 DECL-40 DECL-45	PDF
SMD ACDM Abstract: ACDM ACDM-30 ACDM-35 ACDM-40 ACDM-50 ACDM-60 Text: ACDM Series Advanced CMOS Logic Buffered 5-Tap Delay Modules 74ACT type input is compatible with TTL Electrical Specifications at 25OC Tap Delay Tolerances +/- 5% or 2ns +/- 1ns <13ns 74ACT 5 Tap 14-pin DIP P/N Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5 Low Profile 14-Pin Package	Original	74ACT 14-pin 74LVC ACDM-30 ACDM-35 ACDM-40 ACDM-50 ACDM-60 SMD ACDM ACDM ACDM-30 ACDM-35 ACDM-40 ACDM-50 ACDM-60	PDF
AIDM Abstract: AIDM-11 AIDM-13 AIDM-15 AIDM-20 AIDM-25 AIDM-30 AIDM-35 AIDM-40 AIDM-50 Text: AIDM Series FAST / TTL Buffered 5-Tap Delay Modules Electrical Specifications at 25OC Tap Delay Tolerances +/- 5% or 2ns +/- 1ns <13ns FAST/TTL 14-Pin DIP P/N Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5 Low Profile 14-Pin Package Two Surface Mount Versions FAST/TTL Logic Buffered	Original	14-Pin AIDM-11 AIDM-13 AIDM-15 AIDM-20 AIDM-25 AIDM-30 AIDM-35 AIDM-40 AIDM AIDM-11 AIDM-13 AIDM-15 AIDM-20 AIDM-25 AIDM-30 AIDM-35 AIDM-40 AIDM-50	PDF
74F04 Abstract: DS1004 DS1004M DS1004Z Text: DS1004 DS1004 5-Tap High–Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All–silicon timing circuit • Five equally delayed clock phases per input IN 1 8 Vcc TAP 2 2 7 TAP 1 • Precise tap–to–tap delay tolerances of TAP 4 3 6 TAP 3 GND 4 5 TAP 5	Original	DS1004 DS1004M DS1004Z 74F04 DS1004	PDF
74F04 Abstract: DS1004 DS1004M DS1004Z Text: DS1004 DS1004 5-Tap High–Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All–silicon timing circuit • Five equally delayed clock phases per input IN 1 8 Vcc TAP 2 2 7 TAP 1 • Precise tap–to–tap delay tolerances of TAP 4 3 6 TAP 3 GND 4 5 TAP 5	Original	DS1004 DS1004M DS1004Z 74F04 DS1004	PDF
XAITD Abstract: XAITD-12 XAITD-15 XAITD-20 XAITD-25 XAITD-30 XAITD-35 XAITD-40 XAITD-50 XAITD-60 Text: XAITD Series FAST / TTL Buffered 10-Tap Delay Modules Low Profile 14-Pin Package Two Surface Mount Versions FAST/TTL Logic Buffered Electrical Specifications at 25OC FAST 10 Tap 14-Pin P/N Tap Delay Tolerances +/- 5% or 2ns +/- 1ns <15ns Tap 1 Tap 2 Tap 3	Original	10-Tap 14-Pin XAITD-12 XAITD-15 XAITD-20 XAITD-25 XAITD-30 XAITD XAITD-12 XAITD-15 XAITD-20 XAITD-25 XAITD-30 XAITD-35 XAITD-40 XAITD-50 XAITD-60	PDF
74ls gate symbols Abstract: 74FO4 pin diagram of 74LS "Delay Lines" 74ls series 74LS SERIES cmos logic data DS1010-60 74LS series datasheet 74ls series logic DS1010-200 Text: DS1010 DS1010 10-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay IN1 1 14 VCC NC 2 13 TAP 1 IN 1 16 VCC TAP 2 3 12 TAP 3 NC 2 15 NC • Leading and trailing edge accuracy TAP 4 4 11 NC TAP 2 3 14 TAP 5 TAP 1 • Delay tolerance ±5% or ±2 ns, whichever is greater	Original	DS1010 10-Tap 14-pin 16-pin DS1010 74FO4 74ls gate symbols 74FO4 pin diagram of 74LS "Delay Lines" 74ls series 74LS SERIES cmos logic data DS1010-60 74LS series datasheet 74ls series logic DS1010-200	PDF
74LS Abstract: DS1010 DS1010-100 DS1010-50 DS1010-60 DS1010-75 DS1010-80 DS1010S ds1010-500 Text: DS1010 DS1010 10-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay IN1 1 14 VCC NC 2 13 TAP 1 IN 1 16 VCC TAP 2 3 12 TAP 3 NC 2 15 NC • Leading and trailing edge accuracy TAP 4 4 11 NC TAP 2 3 14 TAP 5 TAP 1 • Delay tolerance ±5% or ±2 ns, whichever is greater	Original	DS1010 10-Tap 14-pin 16-pin 74FO4 74LS DS1010 DS1010-100 DS1010-50 DS1010-60 DS1010-75 DS1010-80 DS1010S ds1010-500	PDF
11ACB50012E Abstract: 11acb10012e 11ACB50112E 14 PIN DIL PACKAGE 11ACB10112E 11ACB20012E 11acb25112e DIL package 11ACB 300C Text: DELAY LINESHASeries 10 Tap 14 pin DIL Package STANDARD PIN-OUT CODE E • Lumped constant • Low profile GND 14 OUT TAP 9 TAP 8 TAP 7 TAP 6 TAP 5 8 O TTL and DTL compatible • Low distortion and low attenuation • High reliability • Auto insertable	Original	11ACB10012E 11ACB20012E 11ACB30012E 11ACB40012E 11ACB50012E 11ACB60012E 11ACB75012E 11ACB10112E 11ACB12112E 11ACB15112E 11ACB50012E 11acb10012e 11ACB50112E 14 PIN DIL PACKAGE 11ACB10112E 11ACB20012E 11acb25112e DIL package 11ACB 300C	PDF
Untitled Abstract: No abstract text available Text: Tap/Isolator Hybrid Tap - Isolator Hybrid Single Stage Dual Stage 1535 nm – 1565 nm 1530 nm – 1570 nm ≤ 0.7 dB ≤ 0.9 dB Parameter Wavelength Range Insertion Loss in Signal Channel for 1% tap ratio Insertion Loss in Tap Channel ≤ 14dB (5% Tap), ≤ 20.8 dB (1% Tap)	Original	SMF-28e.	PDF
Untitled Abstract: No abstract text available Text: Tap/Isolator Hybrid Tap - Isolator Hybrid Single Stage Dual Stage 1535 nm – 1565 nm 1530 nm – 1570 nm ≤ 0.7 dB ≤ 0.9 dB Parameter Operating Wavelength Range Insertion Loss in Signal Channel for 1% tap ratio Insertion Loss in Tap Channel ≤ 14dB (5% Tap), ≤ 20.8 dB (1% Tap)	Original	SMF-28e.	PDF
Untitled Abstract: No abstract text available Text: HYBRID Tap - Isolator Hybrid Tap – Tap Isolator HybridHybrid – Isolator Tap – Isolator Hybrid Features: Features Features Tap – Isolator Features lossinsertion and PDL •Ultra-low insertion loss and PDL •Ultra-low •High isolation insertion loss and PDL	Original	LT062002 LT062002	PDF
VOA MEMS Abstract: VOA dicon dicon Text: MEMS Tap/VOA Hybrid DiCon's MEMS Tap/VOA Hybrid is based on a micro-electromechanical system MEMS chip integrated with a thin film filter. The thin film tap filter couples a portion of the input signal to an output tap fiber while transmitting the rest of the input signal	Original		PDF
GIC-KSMP-KSMP-36 Abstract: No abstract text available Text: Tap Bypass Jumper The Corning Gilbert Tap Bypass Jumper is designed to maintain power and RF integrity through a tap housing when the normal circuit is interrupted by removing the tap face plate. The contact probe is spring loaded axially to accommodate a wide range of tap seizure	Original	GIC-KSMP-KSMP-36) GIC-KSMP-KSMP-36 GIC-KSMP-KSMP-36	PDF

74F04 Abstract: 74LS DS1000 DS1000M DS1000Z Text: DS1000 DS1000 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay • 5 taps equally spaced IN 1 14 Vcc NC 2 13 NC • Delays are stable and precise NC 3 12 TAP 1 TAP 2 4 11 NC NC 5 10 TAP 3 TAP 4 6 9 NC GND 7 8 TAP 5 • Both leading and trailing edge accuracy	Original	DS1000 DS1000 14-PIN 74F04 74F04 74LS DS1000M DS1000Z	PDF
Untitled Abstract: No abstract text available Text: 10K ECL Logic Buffered Delay 16-Pin Modules 5-Tap: DECL Single: FECL Triple: MECL * * Electrical Specifications at 25°C_ 10K ECL 5 Tap P/N Tap Delay Tolerances +/- 5% or 1.5ns +/- 0.8ns <10ns Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5	OCR Scan	16-Pin DECL-10 DECL-12 DECL-15 DECL-20 DECL-25 DECL-30 DECL-35 DECL-40 DECL-45	PDF
Untitled Abstract: No abstract text available Text: 10K ECL Logic Buffered Delay 16-Pin Modules 5-Tap: DECL • Single: FECL • Electrical Specifications at 25°C Electrical Specifications at 25°C Tap Delay Tolerances +/- 5% or 1,5ns +/- 0.8ns <10ns 10K ECL 5 Tap P/N Tap 1 Triple: MECL Tap 2 Tap 3 Tap 4	OCR Scan	16-Pin DECL-10 DECL-12 DECL-15 DECL-20 DECL-25 DECL-30 DECL-35 DECL-40 DECL-45	PDF
Untitled Abstract: No abstract text available Text: DS 1010 DS1010 DALLAS SEMICONDUCTOR 10-Tap Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon time delay IN1 [ " ^3 7 ] vcc • 10 taps equally spaced • Delays are stable and precise NC c ] TAP 1 TAP 2 C ] TAP 3 ] TAP 5 ] TAP 7 TAP 4 C 1 TAP 9 TAP 6 d	OCR Scan	DS1010 10-Tap 14-pin 16-pin 1010S 14-PIl	PDF
DS1010 Abstract: 74LS DS1010-100 DS1010-50 DS1010-60 DS1010-75 DS1010-80 DS1010S dip switch data Text: DS 1010 DALLAS DS1010 10-Tap Silicon Delay Line s e m ic o n d u c t o r FEATURES PIN ASSIGNMENT • All-silicon tim e delay ini r 1 14 V cc NO 2 13 TAP 1 TAP 2 [_ 3 12 TAP 3 4 11 TAP 5 TAP 6 \_ 5 10 TAP 7 TAP 4 6 9 TAP 9 TAP 6 • 10 taps equally spaced • Delays are stable and precise	OCR Scan	DS1010 10-Tap 14-pin 16-pin 11central 74F04 DS1010 74LS DS1010-100 DS1010-50 DS1010-60 DS1010-75 DS1010-80 DS1010S dip switch data	PDF
50A10250 Abstract: 50A10750 50A-10151 50A-10250 218C 300C 50A-10101 50A-10201 50A-10251 50A-10500 Text: DUAL - IN - LINE PACKAGE TOP VIEW □ Schottky TTL compatible □ 10 equally spaced taps □ 14 pin package □ Low profile □ TTL compatible □ Auto insert or surface mount package styles Vcc 14 IN TAP 1 13 TAP 3 12 TAP 5 TAP 7 TAP 9 11 10 9 OUT 8 TAP 2	OCR Scan	0A-10250 0A-10500 0A-10750 0A-10101 0A-10151 0A-10201 0A-10251 0A-10301 0A-10351 0A-10401 50A10250 50A10750 50A-10151 50A-10250 218C 300C 50A-10101 50A-10201 50A-10251 50A-10500	PDF
50A-10500 Abstract: 50A-10201 50A-10250 50A-10101 218C 300C 50A-10151 50A-10251 50A-10750 50A10250 Text: DIGITAL DELAY MODULES 50A, 52A, 52S Series 10 Tap 14 Pin Moulded DIP DUAL - IN - LINE PACKAGE TOP VIEW □ Schottky TTL compatible □ 10 equally spaced taps □ 14 pin package Vcc 14 TAP 1 13 TAP 3 12 TAP 5 11 w TAP 7 10 TAP 9 9 OUT 8 rpns~iirq^nr" Tnq-rrj^rT1	OCR Scan	0A-10250 0A-10500 0A-10750 0A-10101 0A-10151 0A-10201 0A-10251 0A-10301 0A-10351 0A-10401 50A-10500 50A-10201 50A-10250 50A-10101 218C 300C 50A-10151 50A-10251 50A-10750 50A10250	PDF
50A52 Abstract: No abstract text available Text: DIGITAL DELAY MODULES 5QA, 52A, 52S Series 10 Tap 14 Pin Moulded DIP DUAL - IN - LINE PACKAGE TOP VIEW □ Schottky TTL compatible □ 10 equally spaced taps □ 14 pin package Vcc 14 TAP 1 13 TAP 3 12 TAP 5 11 TAP 7 10 TAP 9 9 OUT 8 □ Low profile □ TTL compatible	OCR Scan		PDF
Untitled Abstract: No abstract text available Text: T a p Bypass Jumper The Gilbert Tap Bypass Jumper is designed to maintain power and RF integrity through a tap housing when the normal circuit is interrupted by removing the tap face plate. The contact probe is spring loaded axially to accommodate a wide range of tap seizure mechanisms and	OCR Scan	GIC-KSMP-KSMP-36)	PDF
Untitled Abstract: No abstract text available Text: T a p Bypass Jumper v The Gilbert Tap Bypass Jumper is designed to maintain power and RF integrity through a tap housing when the normal circuit is interrupted by removing the tap face plate. The contact probe is spring loaded axially to accommodate a wide range of tap seizure mechanisms and	OCR Scan	GIC-KSMP-KSMP-36) GIC-KSMP-KSMP-36	PDF

TAP ME Search Results

TAP ME Result Highlights (5)

TAP ME Price and Stock

KAGA FEI America Inc MB85RC64TAPN-G-AMEWE1

Xeltek Inc Lens and Tape Attachment Frame

TAP ME Datasheets Context Search

Untitled

SMD ACDM

AIDM

74F04

74F04

XAITD

74ls gate symbols

74LS

11ACB50012E

Untitled

Untitled

Untitled

VOA MEMS

GIC-KSMP-KSMP-36

74F04

Untitled

Untitled

Untitled

DS1010

50A10250

50A-10500

50A52

Untitled

Untitled