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    Sullins Connector Solutions PTC32DAEN

    CONN HEADER VERT 64POS 2.54MM
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    Sullins Connector Solutions PTC32DBCN

    CONN HEADER R/A 64POS 2.54MM
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    Sullins Connector Solutions PTC32DACN

    CONN HEADER VERT 64POS 2.54MM
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    DigiKey PTC32DACN Bulk 1
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    Sullins Connector Solutions PTC32DAHN

    CONN HEADER VERT 64POS 2.54MM
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    DigiKey PTC32DAHN Bulk 1
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    Sullins Connector Solutions PTC32DFCN

    CONN HEADER VERT 64POS 2.54MM
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    DigiKey PTC32DFCN Bulk 1
    • 1 $3.93
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    TC32D Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    GR-1244-CORE

    Abstract: GR-253-CORE ZL30109 ZL30109QDG ZL30109QDG1
    Text: ZL30109 DS1/E1 System Synchronizer with 19.44 MHz Output Data Sheet Features November 2005 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces • Supports ANSI T1.403 and ETSI ETS 300 011 for


    Original     		ZL30109 GR-1244-CORE ZL30109QDG ZL30109QDG1 GR-253-CORE ZL30109 PDF

    GR-1244-CORE

    Abstract: GR-253-CORE ZL30109 ZL30109QDG ZL30109QDG1 TC65D
    Text: ZL30109 DS1/E1 System Synchronizer with 19.44 MHz Output Data Sheet Features November 2004 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces • Supports ANSI T1.403 and ETSI ETS 300 011 for


    Original     		ZL30109 GR-1244-CORE ZL30109QDG ZL30109QDG1 GR-253-CORE ZL30109 TC65D PDF

    ZL30102

    Abstract: GR-1244-CORE ZL30102QDG ZL30102QDG1
    Text: ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 Data Sheet Features • November 2005 Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock


    Original     		ZL30102 ZL30102QDG ZL30102QDG1 GR-1244-CORE ZL30102 PDF

    Untitled

    Abstract: No abstract text available
    Text: T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Selectable input reference: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44


    Original     		IDT82V3011 TR62411 GR-1244-CORE IDT82V3011 82V3011 PDF

    GR-1244-CORE

    Abstract: GR-253-CORE ZL30109 ZL30109QDG ZL30109QDG1 T110
    Text: ZL30109 DS1/E1 System Synchronizer with 19.44 MHz Output Data Sheet Features April 2010 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces Ordering Information *Pb Free Matte Tin


    Original     		ZL30109 GR-1244-CORE ZL30109QDG1 GR-253-CORE ZL30109 ZL30109QDG T110 PDF

    GR-1244-CORE

    Abstract: GR-253-CORE ZL30106 ZL30106QDG "network interface cards"
    Text: ZL30106 SONET/SDH/PDH Network Interface DPLL Data Sheet Features • • • • • • • • October 2004 Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs Supports output wander and jitter generation specifications for SONET/SDH and PDH


    Original     		ZL30106 GR-1244-CORE GR-253-CORE ZL30106 ZL30106QDG "network interface cards" PDF

    Untitled

    Abstract: No abstract text available
    Text: WAN PLL WITH DUAL REFERENCE INPUTS FEATURES • • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces


    Original     		IDT82V3002 TR62411 GR-1244-CORE com/docs/PSC4029 PDF

    Untitled

    Abstract: No abstract text available
    Text: T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3012 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns per 125 µs


    Original     		TR62411 GR-1244-CORE IDT82V3012 DT82V3012 PVG56) 82V3012 PDF

    Untitled

    Abstract: No abstract text available
    Text: WAN PLL WITH DUAL REFERENCE INPUTS IDT82V3002A FEATURES • • • • • • • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces


    Original     		TR62411 GR-1244-CORE IDT82V3002A freqDT82V3002A PVG56) 82V3002A PDF

    32.768mhz ic

    Abstract: No abstract text available
    Text: WAN PLL WITH SINGLE REFERENCE CLOCK FEATURES • • • • • • • • • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface


    Original     		IDT82V3001 TR62411 GR-1244-CORE 544MHz 048MHz 025ppm 5ns/125 600ns Fr001 32.768mhz ic PDF

    GR-1244-CORE

    Abstract: ZL30102 ZL30102QDG ZL30102QDG1
    Text: ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 Data Sheet Features April 2010 • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock •


    Original     		ZL30102 GR-1244-CORE ZL30102 ZL30102QDG ZL30102QDG1 PDF

    GR-1244-CORE

    Abstract: ZL30100 ZL30100QDC ZL30100QD
    Text: ZL30100 T1/E1 System Synchronizer Data Sheet Features June 2004 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbps and 1544 kbps interfaces • Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces


    Original     		ZL30100 GR-1244-CORE ZL30100 ZL30100QDC ZL30100QD PDF

    C155

    Abstract: GR-1244-CORE IDT82V3155 TR62411
    Text: ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS IDT82V3155 FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 clock, OC-3 port and 155.52 Mbit/s application • Supports ITU-T G.813 Option 1 clocks


    Original     		IDT82V3155 TR62411 GR-1244-CORE PVG56) 82V3155 C155 IDT82V3155 PDF

    Untitled

    Abstract: No abstract text available
    Text: WAN PLL WITH SINGLE REFERENCE INPUT IDT82V3001A FEATURES • • • • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface


    Original     		IDT82V3001A TR62411 GR-1244-CORE ns/125 PVG56) 82V3001A PDF

    GR-1244-CORE

    Abstract: TR62411 PLL 2400 MHZ
    Text: WAN PLL WITH SINGLE REFERENCE INPUT FEATURES • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface


    Original     		TR62411 GR-1244-CORE ns/125 IDT82V3001 com/docs/PSC4029 PLL 2400 MHZ PDF

    GR-1244-CORE

    Abstract: GR1244-CORE ZL30101 ZL30101QDC ZL30101QDG1
    Text: ZL30101 T1/E1 Stratum 3 System Synchronizer Data Sheet Features April 2010 • Supports Telcordia GR-1244-CORE Stratum 3 • Supports G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces Ordering Information ZL30101QDG1 64 Pin TQFP* Trays, Bake & Drypack


    Original     		ZL30101 GR-1244-CORE ZL30101QDG1 GR1244-CORE ZL30101 ZL30101QDC PDF

    GR-1244-CORE

    Abstract: GR-253-CORE MT90866 ZL30105 ZL30105QDG ZL30106 tc84l
    Text: ZL30105 T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110 Data Sheet Features June 2004 • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between the master-clock and the redundant slave-clock • Supports ITU-T G.813 option 1, G.823 for 2048 kbs


    Original     		ZL30105 GR-1244-CORE ZL30105QDG GR-253-CORE MT90866 ZL30105 ZL30105QDG ZL30106 tc84l PDF

    GR-1244-CORE

    Abstract: ZL30102 ZL30102QDG
    Text: ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 Data Sheet Features July 2004 • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock •


    Original     		ZL30102 GR-1244-CORE ZL30102 ZL30102QDG PDF

    GR-1244-CORE

    Abstract: GR1244-CORE IDT82V3011 SSOP56 TR62411
    Text: T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Selectable input reference: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44


    Original     		IDT82V3011 TR62411 GR-1244-CORE IDT82V3011 82V3011 GR1244-CORE SSOP56 PDF

    Untitled

    Abstract: No abstract text available
    Text: WAN PLL WITH SINGLE REFERENCE INPUT IDT82V3001A FEATURES • • • • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface


    Original     		IDT82V3001A TR62411 GR-1244-CORE ns/125 IDT82V3001A 82V3001A PDF

    GR-1244-CORE

    Abstract: ZL30100 ZL30100QDC ZL30100QDG1
    Text: ZL30100 T1/E1 System Synchronizer Data Sheet Features February 2006 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces • Supports ANSI T1.403 and ETSI ETS 300 011 for


    Original     		ZL30100 GR-1244-CORE ZL30100 ZL30100QDC ZL30100QDG1 PDF

    C155

    Abstract: GR-1244-CORE IDT82V3155 SSOP56 TR62411
    Text: ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3155 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns per 125 µs


    Original     		IDT82V3155 56-pin TR62411 GR-1244-CORE IDT82V3155 82V3155 C155 SSOP56 PDF

    GR-1244-CORE

    Abstract: GR1244-CORE IDT82V3001A SSOP56 TR62411
    Text: WAN PLL WITH SINGLE REFERENCE INPUT IDT82V3001A FEATURES • • • • • • • • • • • • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface


    Original     		IDT82V3001A TR62411 GR-1244-CORE ns/125 IDT82V3001A 82V3001A GR1244-CORE SSOP56 PDF

    GR-1244-CORE

    Abstract: IDT82V3012 SSOP56 TR62411
    Text: T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS FEATURES IDT82V3012 • Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1 • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns per 125 µs


    Original     		IDT82V3012 56-pin TR62411 GR-1244-CORE IDT82V3012 82V3012 SSOP56 PDF