TCPT 200 Search Results

RSY160P05

Contextual Info: RSY160P05 Transistors 4V Drive Pch MOSFET RSY160P05 zDimensions Unit : mm zStructure Silicon P-channel MOSFET TCPT (2) zFeatures 1) Low On-resistance. 2) Built-in G-S Protection Diode. 3) Same land pattern as CPT3 (D-PAK). (1) (3) zApplication Switching

Contextual Info: REV, I.OxND. DF CONTACTS -4.0 2.0 X No. o f Positions ± 0.2 2.0 X No. o f C o n tacts - 2-01.2 OPTIONAL TCpT •cpr If | H u_|_u | 1¡1 | | | 2.0 TtpT DATE RELEASED 07/28/02 1,1 REVISED 10/17/02 OJ s s l [ t l H [ t l [ t l [ t i [ t i ( 1 i [ t i [ t i

MSM5432126A

Contextual Info: お客様各位 資料中の「沖電気」「ＯＫＩ」等名称の OKI セミコンダクタ株式会社への変更について 2008 年 10 月 1 日を以って沖電気工業株式会社の半導体事業は OKI セミコン ダクタ株式会社に承継されました。 従いまして、本資料中には「沖電気工業株

MSM54V32126A

Abstract: SSOP64-P-525-0 64TSOP L1526
Contextual Info: お客様各位 資料中の「沖電気」「ＯＫＩ」等名称の OKI セミコンダクタ株式会社への変更について 2008 年 10 月 1 日を以って沖電気工業株式会社の半導体事業は OKI セミコン ダクタ株式会社に承継されました。 従いまして、本資料中には「沖電気工業株

TKF315

Abstract: TKF250 315M355 TMF400 TMF355 TUV1600 32M35-32M63 TC100M200 400M450 bs88 60 amp
Contextual Info: List Numbers and Dimensions i ’ t 1 ’v i TF 12 5 -2 0 0 A ra tin g Extended Motor Range 200M 250 & 200M 315t Rating Am p 125 160 200 List rvumDers F orordering purposes Dimensions m millimetres & inches A B D E F G H J M Fixing Centres TF125 mm 70 00 34 90

AS4LC4M4F1-50JC

Abstract: AS4LC4M4F1-50JI AS4LC4M4F1-50TC AS4LC4M4F1-50TI AS4LC4M4F1-60JC AS4LC4M4F1-60JI AS4LC4M4F1-60TC
Contextual Info: May 2001 AS4LC4M4F1 4Mx4 CMOS DRAM Fast Page 3.3V Family Features • Refresh • Organization: 4,194,304 words × 4 bits • High speed - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh - 50/60 ns RAS access time

Contextual Info: AS4C4M4E1 May 2001 4Mx4 CMOS DRAM EDO family Features • Organization: 4,194,304 words × 4 bits • High speed • TTL-compatible, three-state I/O • JEDEC standard package - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time

Contextual Info: May 2001 AS4LC4M4E1 4Mx4 CMOS DRAM EDO 3.3V Family Features • Refresh - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh • TTL-compatible, three-state I/O • JEDEC standard package - 300 mil, 24/26-pin SOJ

4C4M4FOQ-50JC

Abstract: 4C4M4FOQ-50TC 4C4M4FOQ-60JC TSOP300
Contextual Info: March 2001 AS4C4M4FOQ AS4C4M4F1Q 5V 4M X 4 CMOS QuadCAS DRAM fastpage mode Features • Organization: 4,194,304 words x 4 bits • High speed - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time • Low power consumption

AS4C4M4E1-60JC

Abstract: AS4C4M4E1-50JC AS4C4M4E1-50JI AS4C4M4E1-50TC AS4C4M4E1-50TI AS4C4M4E1-60JI AS4C4M4E1-60TC AS4C4M4E1-60TI
Contextual Info: AS4C4M4E1 May 2001 4Mx4 CMOS DRAM EDO family Features • Organization: 4,194,304 words × 4 bits • High speed • TTL-compatible, three-state I/O • JEDEC standard package - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time

AS4LC4M4E1-60JC

Abstract: AS4LC4M4E1-50JC AS4LC4M4E1-50JI AS4LC4M4E1-50TC AS4LC4M4E1-50TI AS4LC4M4E1-60JI AS4LC4M4E1-60TC AS4LC4M4E1-60TI
Contextual Info: April 2001 AS4LC4M4E1 4Mx4 CMOS DRAM EDO 3.3V Family Features • Refresh - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh • TTL-compatible, three-state I/O • JEDEC standard package - 300 mil, 24/26-pin SOJ

rg802

Abstract: RSA4 Register TG802 hdlc DS215 DS2155 DS26502 rcmf
Contextual Info: Maxim > App Notes > TELECOM Keywords: DS215, DS26502, BITS, T1, E1, J1, SCT Sep 24, 2004 APPLICATION NOTE 3360 DS2155 and DS26502 Software Comparison Abstract: This application note discusses the differences between the DS2155 T1/E1/J1 Single Chip Transceiver

130mA

Contextual Info: G -LINK GLT441L08 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Oct 2001 Rev. 1.0 Features : Description : ∗ ∗ ∗ ∗ Fast access time and cycle time. Low power dissipation. ∗ ∗ ∗ ∗ CAS -Before-RAS Refresh, Hidden Refresh and Test Mode Capability.

4C4M4EOQ-50JC

Abstract: 4C4M4EOQ-50TC 4C4M4EOQ-60JC 4C4M4EOQ-60TC AS4C4M4E1Q-50JC
Contextual Info: March 2001 AS4C4M4EOQ AS4C4M4E1Q 4M ✕ 4 CMOS QuadCAS DRAM EDO family Features • Organization: 4,194,304 words x 4 bits • High speed - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time • Low power consumption

AS4LC4M4E1-60JC

Abstract: AS4LC4M4E0-50JC AS4LC4M4E0-50JI AS4LC4M4E0-50TC AS4LC4M4E0-50TI AS4LC4M4E0-60JC AS4LC4M4E0-60JI
Contextual Info: March 2001 AS4LC4M4E0 AS4LC4M4E1 4Mx4 CMOS DRAM EDO Family Features • Refresh - 4096 refresh cycles, 64 ms refresh interval for AS4LC4M4E0 - 2048 refresh cycles, 32 ms refresh interval for AS4LC4M4E1 - RAS-only or CAS-before-RAS refresh or self-refresh

512Kx1 DRAM

Contextual Info: HY51V4100B Series «HYUNDAI 4M X 1bit CMOS DRAM DESCRIPTION The HY51V4100B is the new generation and fast dynamic RAM organized 4,194,304x1-bit. The HY51V4100B utilizes Hyundai’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide

AN2426

Contextual Info: GM71C16100A LG Semicon Co.,Ltd. 16,777,216 W ORDS x I BIT CMOS DYNAMIC RAM Pin Configuration Description The GM 71C16100A is the new generation dynamic RAM organized 16,777,216 x 1 Bit. GM 71C16100A has realized higher density, higher performance and various functions by utilizing advanced CMOS

Contextual Info: G -LINK GLT440M04 1M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr. 2002 Rev. 2.2 Features : Description : ∗ ∗ ∗ ∗ The GLT440M04 is a high-performance CMOS dynamic random access memory containing 4,194,304 bits organized in a x4 configuration. The GLT440M04 offers page

Contextual Info: January 2001 Advance Information AS4VC256K16EO 2.5V 256K X 16 CMOS DRAM EDO Features • EDO page mode • 512 refresh cycles, 8 ms refresh interval • Organization: 262,144 words x 16 bits • High speed - RAS-only or CAS-before-RAS refresh or self refresh

Contextual Info: G -LINK GLT441L04 1M X 4 CMOS DYNAMIC RAM WITH FAST PAGE MODE Nov. 2001 Rev. 1.0 Features : Description : ∗ ∗ ∗ ∗ The GLT441L04 is a high-performance CMOS dynamic random access memory containing 4,194,304 bits organized in a x4 configuration. The GLT4161L04 has 10 row

MSM5432126A

Contextual Info: Pr E2L0052-17-Y1 el im y 131,072-Word ¥ 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM5432126A is a Graphics DRAM organized in a 131,072-word ¥ 32-bit configuration. The technology used to fabricate the MSM5432126A is OKI's CMOS silicon gate process

MSM54V32128

Contextual Info: Pr E2L0046-17-Y1 el im DESCRIPTION The MSM54V32126/8 is a new generation Graphics DRAM organized in a 131,072-word ¥ 32-bit configuration. The technology used to fabricate the MSM54V32126/8 is OKI's CMOS silicon gate process technology. The device operates with a single 3.3 V power supply.

HM514100

Contextual Info: HM514100L Series Low Power Version 4,194,304-Word x 1-Bit Dynamic Random Access Memory • DESCRIPTION HM514100UP Series The Hitachi HM514100 is a CMOS dynamic RAM organized 4,194,304 word x 1-bit. HM514100 has realized high density, higher performance and various func­

MCM54260BT70

Abstract: 5L4260B MCM54260BJ70 tcpt 1200
Contextual Info: MOTOROLA Order this document by MCM54260B/D SEMICONDUCTOR TECHNICAL DATA MCM54260B MCM5L4260B MCM5S4260B Advance Information 256K x 16 CMOS Dynamic RAM Fast Page Mode – 2 CAS, 1 Write Enable The MCM54260B is a 0.6µ CMOS high–speed dynamic random access memory.