IXF18101
Abstract: ORSPI4-2FE1036C POWR1208 pDS4102-DL2A
Text: SPI4.2 Interoperability Between ORSPI4 and LatticeSC Devices June 2006 Technical Note TN1116 Introduction The System Packet Interface, Level 4, Phase 2 SPI4.2 is a system level interface, published in 2001 by the Optical Internetworking forum (OIF), for packet and cell transfer between a physical layer (PHY) device and a link layer
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Original
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TN1116
OC-192
TN1059,
IXF1810
1-800-LATTICE
IXF18101
ORSPI4-2FE1036C
POWR1208
pDS4102-DL2A
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PDF
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Untitled
Abstract: No abstract text available
Text: LatticeSC/M Family Data Sheet DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
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PDF
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pb127d
Abstract: No abstract text available
Text: LatticeSC/M Family Data Sheet DS1004 Version 02.2, December 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
pb127d
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PDF
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Untitled
Abstract: No abstract text available
Text: LatticeSC/M Family Data Sheet DS1004 Version 01.9, January 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
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PDF
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Untitled
Abstract: No abstract text available
Text: LatticeSC/M Family Data Sheet DS1004 Version 02.0, March 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
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PDF
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PB110C
Abstract: PB124A pt36C SCM15 BA5 904 AF P PL80B PR55D pr94a diode transistor pt36c transistor pt42c
Text: LatticeSC/M Family Data Sheet DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 Features – 1 to 7.8 Mbits memory – True Dual Port/Pseudo Dual Port/Single Port – Dedicated FIFO logic for all block RAM
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Original
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DS1004
DS1004
500MHz
700MHz
600Mbps
125Gbps)
1A-10
1152-ball
1704-ball
PB110C
PB124A
pt36C
SCM15
BA5 904 AF P
PL80B
PR55D
pr94a diode
transistor pt36c
transistor pt42c
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PDF
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PB97A
Abstract: PR45C pr77a
Text: LatticeSC/M Family Data Sheet DS1004 Version 02.4, December 2011 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 Features High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
1A-10
1152-ball
1704-ball
PB97A
PR45C
pr77a
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PDF
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PB80D
Abstract: PR87A PR98A PR96A PB110C pr94a diode pt36C pr77a transistor pt36c transistor pt42c
Text: LatticeSC/M Family Data Sheet DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 Features – 1 to 7.8 Mbits memory – True Dual Port/Pseudo Dual Port/Single Port – Dedicated FIFO logic for all block RAM
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Original
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DS1004
DS1004
500MHz
700MHz
600Mbps
125Gbps)
1A-10
1152-ball
1704-ball
PB80D
PR87A
PR98A
PR96A
PB110C
pr94a diode
pt36C
pr77a
transistor pt36c
transistor pt42c
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PDF
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transistor pt36c
Abstract: pb127d PB110C pr82a PB80D umi u26 BA5 904 AF P PB124A PL84C PR55D
Text: LatticeSC/M Family Data Sheet DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
transistor pt36c
pb127d
PB110C
pr82a
PB80D
umi u26
BA5 904 AF P
PB124A
PL84C
PR55D
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PDF
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