Untitled
Abstract: No abstract text available
Text: Signal Processing Digital converters opto coupler transmitters for signal level shifting, isolating and signal regeneration of HTL or TTL signals HEAG 151, 152, 153, 154 Features – Signal level shifting from HTL TTL or TTL HTL – Isolating signal cables to multiple receivers to avoid
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SN7401
Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Text: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package
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24-lead
SN74S474
SN54S475
SN74S475
SN54S482
SN74S482
LCC4270
SN54490
SN74490
SN54LS490
SN7401
sn29601
SN7449
SN74298
SN74265
MC3021
SN54367
sn74142
signetics 8223
9370c
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Untitled
Abstract: No abstract text available
Text: *SYNERGY PECL/TTL-TTL 1:8 CLOCK DISTRIBUTION CHIP SEMICONDUCTOR FEATURES Clockworks PRELIMINARY SY10/100H646 DESCRIPTION • PECL/TTL-TTL version of popular ECLinPS E111 ■ Meets specifications required to drive highperformance x86 processors ■ Guaranteed low skew specification
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SY10/100H646
SY10H646
SY100H646
28-lead
IVT01
-------300pF
200pF
100pF
0013fi
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Untitled
Abstract: No abstract text available
Text: « PECL/TTL-TTL 1:8 CLOCK DISTRIBUTION CHIP C V M C O rV SEMICONDUCTOR FEATURES Clockworks PRELIMINARY SY10/100H646 DESCRIPTION • PECL/TTL-TTL version of popular ECLìnPS E111 ■ Meets specifications required to drive highperformance x86 processors ■ Guaranteed low skew specification
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SY10/100H646
MC10/100H646
TGG13fil
IVT01
------300pF
200pF
100pF
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Untitled
Abstract: No abstract text available
Text: M OTOROLA M C 10H 646 M C 100H 646 Product Preview PEC L/TTL-TTL 1:8 C lo ck D istrib u tio n Chip PECL/TTL-TTL 1:8 CLOCK DISTRIBUTION CHIP The MC1 OH/100H646 is a single supply, low skew translating 1:8 clock driver. Devices in the Motorola ‘H600 translator series utilize the 28-lead PLCC for
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OH/100H646
28-lead
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signal path designer
Abstract: No abstract text available
Text: PRELIMINARY D E V IC E S P E C IF IC A T IO N 320000 SERIES ECL/TTL "TURBO" LOGIC ARRAYS 020000 FEATURES PERFORMANCE SUMMARY PARAMETER Typical gate delay* Maximum toggle frequency Maximum TTL input frequency Maximum TTL output frequency Maximum ECL input frequency
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/D1203-0589
signal path designer
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Untitled
Abstract: No abstract text available
Text: CY10E383 CY101E383 a CYPRESS ~ SEMICONDUCTOR ~ ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional D escription • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpD TTL-to-ECL — 3.5 ns tpD ECL-to-TTL • Low skew < ± 1 ns
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CY10E383
CY101E383
10K/10KH
10K/10KH
CY10/101E383
84-pin
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5D6 diode
Abstract: Power PQFP 64 10e383 Q809
Text: CY10E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpj) TTL-to-ECL — 3.5 ns tpj) ECL-to-TTL • Low skew < ± 1 ns • Can operate on single +5V supply
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CY10E383
CY101E383
80-pin
CY10/101E383
5D6 diode
Power PQFP 64
10e383
Q809
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Untitled
Abstract: No abstract text available
Text: CY10E383 CY101E383 CYPRESS SEMICONDUCTOR ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpu TTL-to-ECL — 3.5 ns tpu ECL-to-TTL • Low skew < ± 1 ns • Can operate on single +5V supply
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CY10E383
CY101E383
80-pin
CY10/101E383
CY10E383â
80-Lead
84-Lead
CY10E383
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CY101E383
Abstract: diode SKE 39
Text: W r CY10E383 CY101E383 CYPRESS ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • B iC M O S for optim um speed/power • H igh speed max. — 2.5 n s Ipu TTL-to-EC L — 3.5 n s tpo EC L-to-TTL The CY10/101E383 is a new-generation
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CY10E383
CY101E383
80-pin
CY10/101E383
CY10E383â
84-Lead
80-Lead
CY101E383
diode SKE 39
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MC10804
Abstract: MC10806 ao65
Text: MOTOROLA MC10804 MC10805 BIDIRECTIONAL TRANSCEIVER WITH LATCH The MC10804 and MC10805 are inverting bidirectional trans ceivers that interface MECL logic levels with TTL logic levels. Data can be transferred directly in either direction MECL -*•TTL or TTL
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MC10804
MC10805
MC10805
16-pln
20-pin
MC10806
ao65
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CY7B185
Abstract: CY7B922 clock buffer FITS CY7B991 CY7B992 EME-6300H SM23B CY7B991-LMB
Text: Qualification Report February, 1994 QTP# 92202&93462 Version 2.0 PROGRAMMABLE SKEWCLOCK BUFFER CY7B991 TTL CY7B992 (CMOS) QUALIFICATION REPORT February, 1994 Version 2.0 QTP # 92202/93462 PROGRAMMABLE SKEW CLOCK BUFFER CY7B991 (TTL) CY7B992 (CMOS) CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA:
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CY7B991
CY7B992
CY7B991
JEDEC22,
30PSIA
CY7B185
CY7B922
clock buffer FITS
CY7B992
EME-6300H
SM23B
CY7B991-LMB
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Untitled
Abstract: No abstract text available
Text: Processor Interface Components—QSpan User Manual 4 Signals and DC Characteristics 4.1 Terminology The abbreviations used in this chapter are defined below. Two-state output Tristate output Bidirectional Input Output Open Drain Input with TTL threshold TTL Schmitt trigger input
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A117I
208-Pin
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signal path designer
Abstract: No abstract text available
Text: PRELIMINARY DEVICE SPECIFICATION Q20000 SERIES ECL/TTL TURBO" LOGIC ARRAYS 020000 FEATURES • Up to 24000 gates, channelless architecture • 100ps equivalent gate delays • Ultra low power ,5-1.0mW/gate • 10K, 10KH, 100K ECL and mixed ECL/TTL capability
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Q20000
100ps
SA/D1203-1089
signal path designer
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ITT401AC
Abstract: SOIC-14
Text: SP4T SWITCH WITH DIRECT TTL CONTROL AND SINGLE POSITVE SUPPLY ITT401AC FEATURES • • • • • Single Positive Supply +8V Direct TTL input On-Chip Decoder Logic Low Power Consumption Non-Reflective Ports DESCRIPTION ADVANCED INFORMATION GND J3 GND J1
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ITT401AC
SOIC-14
ITT401AC
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181-D
Abstract: AD 157 Y AD17 SCL23
Text: Processor Interface Components—QSpan User M anual 4 Signals and DC Characteristics 4.1 Terminology The abbreviations used in this chapter are defined below. Two-state output Tristate output Bidirectional Input Output Open Drain Input with TTL threshold TTL Schmitt trigger input
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b560101
208-Pin
181-D
AD 157 Y
AD17
SCL23
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d15181
Abstract: QSpan AD899 Tundra QSpan 181-D AD17 qspan top mark
Text: Processor Interface Components—QSpan User M anual 4 Signals and DC Characteristics 4.1 Terminology The abbreviations used in this chapter are defined below. Two-state output Tristate output Bidirectional Input Output Open Drain Input with TTL threshold TTL Schmitt trigger input
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b560101
low-l172.
208-Pin
d15181
QSpan
AD899
Tundra QSpan
181-D
AD17
qspan top mark
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j934
Abstract: No abstract text available
Text: SP8T Switch with Direct TTL Control and Single Positive Supply ITTS801AR FEATURES • • • • • ADVANCED INFORMATION TSSOP24 Single Positive Supply 8V Direct TTL input On-Chip Decoder Logic Low Power Consumption Non-Reflective Ports DESCRIPTION MAXIMUM RATINGS (T
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j934
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Untitled
Abstract: No abstract text available
Text: P54/74FCT3973C/D 3.3 VOLT OCTAL TRANSPARENT LATCHES 5.0 TO 3.3 VOLT TRANSLATOR FEATURES • Function and Drive Compatible with the Fastest TTL Logic ■ Inputs and Outputs Interface with TTL Logic Levels ■ 3.3V ± 0.2V Power Supply and CMOS for Lowest
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P54/74FCT3973C/D
FCT3973
I973C
1973D
MIL-STD-883
AE1509-5
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ax 3003
Abstract: meab 1N3064 1N916 M38510 76l70
Text: MIL-M-38510/28B USAF 2 August 1974-SUPERSEDING MIL-M-38510/28(USAF) 21 August 1972 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL TTL, LOW POWER SHIFT REGISTERS MONOLITHIC SILICON 1. SCOPE 1.1 Scope• This specification covers the requirements for monolithic silicon, TTL,
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MIL-M-38510/28B
MIL-M-38510/28
M38510
54L95
54L164
93L28
93L00
76L70
5962-F056)
ax 3003
meab
1N3064
1N916
M38510
76l70
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Untitled
Abstract: No abstract text available
Text: P54/74FCT3157C/D — P54/74FCT3158C/D 3.3 VOLT DATA SELECTOR/MULTIPLEXER 7$ FEATURES Function and Drive Compatible with the Fastest TTL Logic Inputs and Outputs Interface with TTL Logic Levels 3.3V ± 0.2V Power Supply and CMOS for Lowest Power Dissipation
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P54/74FCT3157C/D
P54/74FCT3158C/D
P54/7
FCT3157C/Dâ
P54/74
FCT3158C/D
MIL-STD-883
AE1744-2
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Untitled
Abstract: No abstract text available
Text: SP4T Switch with Direct TTL Control and Single Positive Supply ITTS401AC FEATURES • • • • • ADVANCED INFORMATION SOIC 14 Single Positive Supply +8V Direct TTL input On-Chip Decoder Logic Low Power Consumption Non-Reflective Ports DESCRIPTION MAXIMUM RATINGS (T
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ITTS401AC
SOIC-14
27ref
10ref
057ref
050ref
004ref
MS-012.
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Untitled
Abstract: No abstract text available
Text: P54/74FCT3373C/D 3.3 VOLT OCTAL TRANSPARENT LATCHES WITH 3-STATE OUTPUTS FEATURES • Function and Drive Compatible with the Fastest TTL Logic ■ Edge-rate Control Circuitry for Significantly Reduced Switching Noise Characteristics ■ Inputs and Outputs Interface with TTL Logic
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P54/74FCT3373C/D
FCT3373
FCT3373D
J373C
I373D
AE1747-4
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Untitled
Abstract: No abstract text available
Text: P54/74FCT3157C/D — P54/74FCT3158C/D 3.3 VOLT DATA SELECTOR/MULTIPLEXER FEATURES • Function and Drive Compatible with the Fastest TTL Logic ■ Inputs and Outputs Interface with TTL Logic Levels ■ 3.3V + 0.2V Power Supply and CMOS for Lowest Power Dissipation
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P54/74FCT3157C/D
P54/74FCT3158C/D
FCT3157
FCT315
P54/74FCT3157C/D--F54/74FCT3158C/D_
AE1744-2
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