74LS08 fan-in
Abstract: 74LS398 74LS273 74LS14 Hex Inverter definition MC74F579 74LS181 74ls795 74LS299 Decade Up/Down counter 3 State ttl buffer 74LS245
Text: Selection Information FAST/LS TTL 1 Circuit Characteristics 2 Design Considerations, Testing and Applications Assistance Form 3 FAST Data Sheets 4 LS Data Sheets 5 Reliability Data 6 Package Information Including Surface Mount 7 FAST AND LS TTL DATA CLASSIFICATION
|
Original
|
PDF
|
81LS96)
81LS97)
81LS98)
74LS08 fan-in
74LS398
74LS273
74LS14 Hex Inverter definition
MC74F579
74LS181
74ls795
74LS299
Decade Up/Down counter 3 State
ttl buffer 74LS245
|
IN4004
Abstract: HP2731 7912 regulator IN4004 diode STEbus hp2731 512 diode in4004 arcom STEbus RES680R single action solenoid
Text: STE-SD16LP 2192-08788-000-000 STE-SD16LP Introduction A single Eurocard with STEbus interface provides isolated drive for up to sixteen low voltage solenoids or other power loads. An eight bit port configurable for input or output with TTL buffer drive capability is also included.
|
Original
|
PDF
|
STE-SD16LP
IN4004
HP2731
7912 regulator
IN4004 diode
STEbus
hp2731 512
diode in4004
arcom STEbus
RES680R
single action solenoid
|
FZH115B
Abstract: fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
Text: Digital I.C.s, 74INTEGRATED CIRCUITS DIGITAL TTL, 74LS & 74HC Series Quad 2-input NAND gate Quad 2-input NAND gate, open collector Quad 2-input NOR gate Quad 2-input NOR gate, open collector Hex inverter Hex inverter, O/C collector Hex inverter, Buffer 30V O/P
|
Original
|
PDF
|
74INTEGRATED
Line-to-10
150ns
16-DIL
150ns
18-pin
250ns
300ns
FZH115B
fzh261
FZK105
FZH131
FZJ111
FZH115
FZH205
Multiplexer IC 74151
FZH265B
74LS104
|
74LS245 application
Abstract: logic diagram of 74LS245 74ls245 74ls245 motorola TTL 5400 motorola SN54/74LS245 751d-03 SN54LSXXXJ SN74LSXXXN motorola TTL 5400
Text: SN54/74LS245 OCTAL BUS TRANSCEIVER The SN54 / 74LS245 is an Octal Bus Transmitter/Receiver designed for 8-line asynchronous 2-way data communication between data buses. Direction Input DR controls transmission of Data from bus A to bus B or bus B to bus A depending upon its logic level. The Enable input (E) can be used
|
Original
|
PDF
|
SN54/74LS245
74LS245
74LS245 application
logic diagram of 74LS245
74ls245 motorola
TTL 5400 motorola
SN54/74LS245
751d-03
SN54LSXXXJ
SN74LSXXXN
motorola TTL 5400
|
74ls245
Abstract: 74LS245 application logic diagram of 74LS245 TTL 74ls245 SN54LSXXXJ SN74LSXXXN LS 74LS245
Text: SN54/74LS245 OCTAL BUS TRANSCEIVER The SN54 / 74LS245 is an Octal Bus Transmitter/Receiver designed for 8-line asynchronous 2-way data communication between data buses. Direction Input DR controls transmission of Data from bus A to bus B or bus B to bus A depending upon its logic level. The Enable input (E) can be used
|
Original
|
PDF
|
SN54/74LS245
74LS245
CERAMI70
74LS245 application
logic diagram of 74LS245
TTL 74ls245
SN54LSXXXJ
SN74LSXXXN
LS 74LS245
|
74LS82
Abstract: 74LS176 74LS94 74LS286 74ls150 74LS177 74LS116 74ls198 7400 TTL 74ls521
Text: GOULD 4055916 GOULD SEMICONDUCTOR SEMICONDUCTOR DIV DIV 03E D | 03E MDSSTlb 09920 D UCICmEU T-4 3I-V 7400 TTL Cells •> GOULD CM OS Gate Array and Standard Cell Library Electronics Features General Description • Over 200 functions available. 7400 TTL Cells, a member of Gould’s EXPERT ASIC
|
OCR Scan
|
PDF
|
|
Untitled
Abstract: No abstract text available
Text: LS TTL DN74LS Series DN74LS245 DN74LS245 Octal Bus Transceivers with 3-state Outputs H Description P -3 D N 74LS245 contains eight bus transm itter/reciver circuits w ith non-inverted o utputs. • Features • B idirectional transfer or separation capability for tw o 8-bit
|
OCR Scan
|
PDF
|
DN74LS
DN74LS245
74LS245
20-pin
|
ttl 7447
Abstract: TTL 7446 TTL 7448 7447 ttl logic diagram of 74LS245 74LS245 ttl 74ls47 74IS244 74ILS540 74LS245 latch
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS D IG ITAL-TTL D74 54LS/74LS241 D73 54LS/74LS240 V cc E2 VCC É2 I5IR RRR R RRR R I3IRRRRRRRRR LJ Ul'lil lil isJ' HI lil" 111 lil bsl D80 54LS/74LS540 D79 54LS/74LS245 V cc E Bo Bi B2 B3 B4 B5 B6 B7 Vcc I»1RRRRRRRRR LJU JllJLlJlllLllU JLlJLlllH l
|
OCR Scan
|
PDF
|
54LS/74LS240
54LS/74LS241
54LS/74LS242
54LS/74LS243
54LS/74LS244
54LS/74LS245
54LS/74LS540
74LS245
74ILS540
74ILS541
ttl 7447
TTL 7446
TTL 7448
7447 ttl
logic diagram of 74LS245
ttl 74ls47
74IS244
74LS245 latch
|
DN74LS245
Abstract: MA161
Text: DN74LS245 LS TTL DN74LS Series DN74LS245 ro 74LS^4-S' O ctal Bus T r a n sc e iv e r s w ith 3 -sta te O u tp u ts • Description P-3 D N 74LS245 contains eight bus transm itter/receiver circuits with non-inverted outputs. ■ Features • • • • •
|
OCR Scan
|
PDF
|
DN74LS
DN74LS245
DN74LS245
400mV
-15mA)
MA161
|
SN74ALS123
Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Text: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS
|
OCR Scan
|
PDF
|
MIL-M-38510
SN74ALS123
SN7401
74LS424
54175
SN74298
SN74265
SN74LS630
SN74LS69
National Semiconductor Linear Data Book
Transistor AF 138
|
transistor cross reference
Abstract: MPT3N40 Westinghouse SCR handbook LT 8224 ZENER DIODE sje389 N9602N npn transistor RCA 467 TFK 7 segment displays PUT 2N6027 delco 466
Text: C K TBD DOLLY LIST LOGO LIST SAFETY & RELIABLTY TEK PN SYSTEM II DIGITAL IC's MEMORIES. MOS. CM OS.ECL. TTL MICROPROCESSOR SPECIAL FUNCTION IC's DIGITAL / LINEAR ARRAYS LINEAR IC'S (PURCH) TEK-MADE IC’s 3 IC's INDEX (COLORED PGS) INCL PRGMD. SCRND.ETC
|
OCR Scan
|
PDF
|
|
floppy controller 44 pin
Abstract: No abstract text available
Text: ST84C72 ^STARTECH Printed September 7, 1994 IDE INTERFACE WITH I/O DECODE DESCRIPTION PLCC package The ST84C72 is designed to replace all necessary TTL logics for 16 bit IDE interface and decode logic for floppy controller and serial / parallel I/O ports. A select
|
OCR Scan
|
PDF
|
ST84C72
ST84C72
ST84C72.
floppy controller 44 pin
|
74LS244 diagram
Abstract: fairchild 741 74LS244 E105 IL 741 74S140 TTL 74LS244 74LS245
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D74 54LS/74LS241 D73 54LS/74LS240 V cc E2 VCC I5IR RRR R RRR R É2 I3IRRRRRRRRR LJ U l'lil lil isJ' HI lil" 111 lil bsl D80 54LS/74LS540 D79 54LS/74LS245 Vcc E Bo Bi B2 B3 B4 B5 B6 B7 Vcc I»1RRRRRRRRR L J U J llJ L lJ lllL llU J L lJ L lllH l
|
OCR Scan
|
PDF
|
54LS/74LS240
54LS/74LS241
54LS/74LS242
54LS/74LS243
54LS/74LS244
54LS/74LS245
54LS/74LS540
74LS245
74ILS540
74ILS541
74LS244 diagram
fairchild 741
74LS244
E105
IL 741
74S140
TTL 74LS244
|
TTL 7404
Abstract: 7404 TTL TTL 7401 nand ttl 7400 TTL 741 TTL 7414 74IS244 CI 74LS04 TTL 7400 CI 74LS00
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012,
|
OCR Scan
|
PDF
|
54H/74H04,
54S/74S04,
54LS/74LS04,
9S05A,
54H/74H05,
54S/74S05,
54L8/74LS05,
54LS/74LS14,
54H/74H00,
54S/74S00,
TTL 7404
7404 TTL
TTL 7401
nand ttl 7400
TTL 741
TTL 7414
74IS244
CI 74LS04
TTL 7400
CI 74LS00
|
|
|
7404 TTL CMOS
Abstract: TTL 7400 fairchild TTL 74h04 7404 ttl inverter TTL 7404 fairchild 9016 CI 74LS00 TTL 7404 fairchild 74H00 TTL TTL 9016 fairchild TTL 7401
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012,
|
OCR Scan
|
PDF
|
54H/74H04,
54S/74S04,
54LS/74LS04,
9S05A,
54H/74H05,
54S/74S05,
54L8/74LS05,
54LS/74LS14,
54H/74H00,
54S/74S00,
7404 TTL CMOS
TTL 7400 fairchild
TTL 74h04
7404 ttl inverter
TTL 7404 fairchild 9016
CI 74LS00
TTL 7404 fairchild
74H00 TTL
TTL 9016 fairchild
TTL 7401
|
TTL 7410
Abstract: TTL 7401 TTL 7420 IC TTL 74LS00 TTL 7404 fairchild 9016 74LS00 TTL TTL 74LS04 TTL 7400 fairchild 7400 ecl inverter TTL 74h04
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012,
|
OCR Scan
|
PDF
|
54H/74H04,
54S/74S04,
54LS/74LS04,
9S05A,
54H/74H05,
54S/74S05,
54L8/74LS05,
54LS/74LS14,
54H/74H00,
54S/74S00,
TTL 7410
TTL 7401
TTL 7420
IC TTL 74LS00
TTL 7404 fairchild 9016
74LS00 TTL
TTL 74LS04
TTL 7400 fairchild
7400 ecl inverter
TTL 74h04
|
vl16c552
Abstract: lpt port direction bit 5
Text: VLSI Tech n o lo gy , in c . VL16C552 DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO FEATURES • Three-state TTL drive for the data and control bus on each channel • IBM PC/AT -compatible • Two VL16C550 ACEs • Hardware and software compatible with VL16C452 and VL16C452B
|
OCR Scan
|
PDF
|
VL16C552
VL16C550
VL16C452
VL16C452B
VL16C552
lpt port direction bit 5
|
74HCT245
Abstract: HCT245d ir 643
Text: S G S -T H O M S O N I0 S M54HCT245/640/643 M74HCT245/640/643 OCTAL BUS TRANSCEIVER 3-STATE HCT245 NON INVERTING, HCT640 INVERTING, HCT643 INVERTING/NON INVERTING • LOW POWER DISSIPATION Icc = 4/iA (MAX.) at TA = 25°C ■ COMPATIBLE WITH TTL OUTPUTS
|
OCR Scan
|
PDF
|
M54HCT245/640/643
M74HCT245/640/643
HCT245
HCT640
HCT643
54/74LS245/640/643
HCT245,
HCT640,
M54/74HCT245/640/643
74HCT245
HCT245d
ir 643
|
Untitled
Abstract: No abstract text available
Text: r z 7 SG S TH O M SO N ^ 7 #„ liM»g[LgCT»OigS M54HCT245/640/643 M74HCT245/640/643 OCTAL BUS TRANSCEIVER 3-STATE HCT245 NON INVERTING, HCT640 INVERTING, HCT643 INVERTING/NON INVERTING • LOW POWER DISSIPATION lCC = 4fiA (MAX.) at Ta = 25°C ■ COMPATIBLE WITH TTL OUTPUTS
|
OCR Scan
|
PDF
|
M54HCT245/640/643
M74HCT245/640/643
HCT245
HCT640
HCT643
54/74LS245/640/643
M54HCTXXX
M74HCTXXX
|
ttl 741
Abstract: 1. IC 74IS244 74LS244 diagram Fairchild 96106 741 16 PIN 74S140 E105 74S40
Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS D IG ITA L-TTL D82 54LS/74LS78 D81 54LS/74LS541 V cc |S5| RSj FSI F7| F»l FS1 j j j j F5I Fä| FI j j j SD SD J Q J Q — e Q 5— 9 b C CP CP K >— 12 Q K CD CD LlI lil LiJ Lil LiTIU LzJ LlI üü bsJ QNO 9 3 4 li 5 D85
|
OCR Scan
|
PDF
|
54LS/74LS541
54LS/74LS78
54LS/74LS168,
54LS/74LS169
54LS/74LS490
54LS/74LS373
54LS/74LS374
54LS/74LS256
74LS245
74ILS540
ttl 741
1. IC 74IS244
74LS244 diagram
Fairchild 96106
741 16 PIN
74S140
E105
74S40
|
54LS245
Abstract: No abstract text available
Text: SN54LS245, SN44LS245 OCTAL BUS TRANSCEIVERS WITH 3 STATE OUTPUTS OCTOBER 1976 —REVISED MARCH 1988 Bi-directional Bus Transceiver in a HighDensity 20-Pin Package SN 54LS245 . . J OR W PACKAGE SN 74LS245 . . . DW OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines Directly
|
OCR Scan
|
PDF
|
SN54LS245,
SN44LS245
20-Pin
54LS245
74LS245
SN54LS245
SN74LS245
54LS245
|
74LS245
Abstract: 74LS TTL 245
Text: MOTOROLA SN54/74LS245 OCTAL BUS TRANSCEIVER The SN 54/74LS 245 is an Octal Bus Transmitter/Receiver designed for 8-line asynchronous 2-way data communication between data buses. Direction Input DR controls transmission of Data from bus A to bus B or bus
|
OCR Scan
|
PDF
|
SN54/74LS245
54/74LS
74LS245
74LS TTL 245
|
pj 54 diode
Abstract: PJ 74 DIODE 74ls245 logic diagram
Text: M M O TO RO LA D ES C R IP T IO N — The SN 54LS/74LS245 is an Octal Bus Transmitter/ Receiver designed for 8-line asynchronous 2-way data communication between data buses. Direction Input (DR) controls transmission of Data from bus A to bus B or bus B to bus A depending upon its logic level. The
|
OCR Scan
|
PDF
|
54LS/74LS245
pj 54 diode
PJ 74 DIODE
74ls245 logic diagram
|
ic 74ls245
Abstract: No abstract text available
Text: Ä MOTOROLA SN54LS245 SN74LS245 D E SC R IPTIO N — Th eSN 54LS/74LS245 is an Octal BusTransmitter/ Receiver designed for 8-line asynchronous 2-way data communication between data buses. Direction Input (DR) controls transmission of Data from bus A to bus Bor bus B to bus A depending upon its logic level. The
|
OCR Scan
|
PDF
|
54LS/74LS245
SN54LS245
SN74LS245
ic 74ls245
|
