TTL LOGIC Search Results

TTL LOGIC Result Highlights (5)

Part	Manufacturer	Description
SNJ5480J	Rochester Electronics LLC	Adder/Subtractor, TTL, CDIP14,
5480FM	Rochester Electronics LLC	5480 - Multiplier, TTL, CDFP14
9317CDC	Rochester Electronics LLC	9317 - Decoder/Driver, TTL, CDIP16
54H62FM	Rochester Electronics LLC	54H62 - Gate, TTL, CDFP14
5496J/B	Rochester Electronics LLC	5496 - Shift Register, 5-Bit, TTL

TTL LOGIC Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: IDT74GTLP816 GTLP / TTL 1:2 / 1:6 CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE GTLP/TTL 1:2/1:6 CLOCK DRIVER FEATURES: • • • • • • • • DESCRIPTION: 5V or 3.3V operation Interface between GTLP and TTL logic levels GTLP to TTL 1:6 fanout TTL to GTLP 1:2 fanout	Original	IDT74GTLP816 IDT74GTLP	PDF
Untitled Abstract: No abstract text available Text: IDT74GTLP816 GTLP / TTL 1:2 / 1:6 CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE GTLP/TTL 1:2/1:6 CLOCK DRIVER FEATURES: • • • • • • • • DESCRIPTION: 5V or 3.3V operation Interface between GTLP and TTL logic levels GTLP to TTL 1:6 fanout TTL to GTLP 1:2 fanout	Original	IDT74GTLP816 IDT74GTLP	PDF
IDT74GTLP816 Abstract: No abstract text available Text: IDT74GTLP816 GTLP / TTL 1:2 / 1:6 CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE GTLP/TTL 1:2/1:6 CLOCK DRIVER FEATURES: • • • • • • • DESCRIPTION: Interface between GTLP and TTL logic levels GTLP to TTL 1:6 fanout TTL to GTLP 1:2 fanout Edge Rate Control Circuit reduces output noise on GTLP port	Original	IDT74GTLP816 IDT74GTLP IDT74GTLP816	PDF
MSI Logic Abstract: UT54ACS14E ut54acts541e UT54ACTS02E UT54ACS14 Tri-State Buffer CMOS cmos msi data book cmos TTL LOGIC DATA BOOK UT54ACS373 Text: Aeroflex MSI Logic IBIS model Buffer Identification 4/16/2009 Tri-State Devices Input Buffer CMOS TTL Output Buffer 8mA 8mA UT54ACS273 UT54ACTS04 CMOS CMOS E TTL TTL (E) 8mA 8mA 8mA 8mA UT54ACS273 UT54ACS02E UT54ACTS04 UT54ACTS08E CMOS TTL 8mA 8mA UT54ACS273	Original	UT54ACS273 UT54ACTS04 UT54ACS02E UT54ACTS08E MSI Logic UT54ACS14E ut54acts541e UT54ACTS02E UT54ACS14 Tri-State Buffer CMOS cmos msi data book cmos TTL LOGIC DATA BOOK UT54ACS373	PDF
IC TTL 74LS00 Abstract: TTL LS 7400 IC TTL 74 ls 04 7400 fan-out cmos 7400 fan-out TTL 7400 catalog TTL 74ls00 TTL 7400 rise and fall time of ic 74ls00 74LS00 gate Text: Design Considerations, Testing and Applications Assistance Form FAST AND LS TTL FAST AND LS TTL DATA 3-1 3 DESIGN CONSIDERATIONS SELECTING TTL LOGIC. TTL Families may be mixed in a system for optimum performance. For instance, in new designs, ALS would commonly be used in non-critical speed paths to minimize power consumption while FAST TTL would be used in high	Original		PDF
CY101E383 Abstract: E383 R2170 ecl 84 Text: E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL Functional Description The CY101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-perfor-	Original	CY101E383 CY101E383 8-A-00023 E383 R2170 ecl 84	PDF
2n2222 fairchild Abstract: 74OL60XX Text: 74OL6000, 74OL6001, 74OL6010, 74OL6011 Optoplanar High-Speed Logic-to-Logic Optocouplers LSTTL to TTL Buffer TTL Inverter CMOS Buffer CMOS Inverter Description 74OL6000 74OL6001 74OL6010 74OL6011 Features • Industry first LSTTL to TTL and LSTTL to CMOS	Original	74OL6000, 74OL6001, 74OL6010, 74OL6011 74OL6000 74OL6001 2n2222 fairchild 74OL60XX	PDF
ttlpd Abstract: 125OC TTLPD-10 TTLPD-10M TTLPD-15 TTLPD-15M TTLPD-20 TTLPD-25 TTLPD-30 Text: TTLPD Series FAST / TTL Pulse Width Discriminator Modules Electrical Specifications at 25OC FAST / TTL Pulse Width Discriminator Modules 14-Pin Package Commercial and Mil-Grade Versions FAST/TTL Logic Buffered Pass Pulse Widths above & suppress Pulses below Nominal Value	Original	14-Pin TTLPD-10M TTLPD-15M TTLPD-20 TTLPD-20M TTLPD-25 TTLPD-25M TTLPD-30 TTLPD-30M TTLPD-35 ttlpd 125OC TTLPD-10 TTLPD-10M TTLPD-15 TTLPD-15M TTLPD-20 TTLPD-25 TTLPD-30	PDF
HLT28 Abstract: HT28 KLT28 KT28 MC100ELT28 MC10ELT28 MC10ELT28D Text: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading	Original	MC10ELT28, MC100ELT28 HLT28 KLT28 MC10ELT28/D HLT28 HT28 KLT28 KT28 MC100ELT28 MC10ELT28 MC10ELT28D	PDF
HLT28 Abstract: KLT28 MC100 MC100ELT28 MC10ELT28 transistor k 4110 Text: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading	Original	MC10ELT28, MC100ELT28 HLT28 KLT28 MC10ELT28/D HLT28 KLT28 MC100 MC100ELT28 MC10ELT28 transistor k 4110	PDF
F100K Abstract: SY100S324 SY100S324DC SY100S324FC SY100S324JC SY100S324JCTR Text: SYNERGY SY100S324 LOW POWER HEX TTL-to-ECL TRANSLATOR SEMICONDUCTOR SYNERGY SY100S324 SEMICONDUCTOR FEATURES DESCRIPTION • Max. propagation delay of 1.4ns The SY100S324 is a hex translator designed to convert TTL logic levels to 100K ECL levels. The inputs are TTL	Original	SY100S324 SY100S324 00S324 SY100S324DC D24-1 SY100S324FC F24-1 SY100S324JC J28-1 F100K SY100S324DC SY100S324FC SY100S324JC SY100S324JCTR	PDF
Untitled Abstract: No abstract text available Text: 14 PIN TTL SCHOTTKY SQUARE WAVE GENERATOR 53A SERIES FEATURES • • • • • 14-PIN PACKAGE. 10 TTL FAN-OUT CAPACITY. TTL SCHOTTKY INTERFACED. OUTPUT FREQUENCY TOLERANCE:±2%. OUTPUT DUTY CYCLE:50%±5% ELECTRICAL CHARACTERISTICS IIH Logic”1” Input Current	Original	14-PIN 25Vdc 3A-002 3A-003 3A-004 3A-005 3A-010 3A-015 3A-020 3A-025	PDF
GTLP8T306 Abstract: MTC24 Text: March 1998 GTLP8T306 8-Bit TTL-to-GTLP Bus Transceivers Preliminary General Description Features The GTLP8T306 is an 8-bit bus transceiver that provides TTL to GTLP signal level translation. The device provides a high speed interface between cards operating at TTL logic	Original	GTLP8T306 GTLP8T306 MTC24	PDF
Untitled Abstract: No abstract text available Text: 100325 100325 Low Power Hex ECL-to-TTL Translator Literature Number: SNOS129A 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit	Original	SNOS129A F100K	PDF

Untitled Abstract: No abstract text available Text: IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER FEATURES: • • • • • DESCRIPTION: Bidirectional interface between GTLP and TTL logic levels Edge Rate Control Circuit reduces output noise	Original	IDT74GTLP16612 18-BIT	PDF
GTLP16612 Abstract: IDT74GTLP16612 Text: IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER FEATURES: • • • • • DESCRIPTION: Bidirectional interface between GTLP and TTL logic levels Edge Rate Control Circuit reduces output noise	Original	IDT74GTLP16612 18-BIT GTLP16612 IDT74GTLP16612	PDF
100324PC Abstract: 100324QC 100324QI 100324SC M24B MS-013 N24E V28A 100124 100324 Text: Revised August 2000 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible with standard or Schottky TTL. A common Enable	Original		PDF
740L6000 Abstract: transistor c2026 c2026 c2026 transistor data 740L6010 transistor equivalent c2026 740L6011 C2026 TRANSISTOR 740L6001 c2037 Text: HIGH-SPEED LOGIC-TO’LOGIC OPTOCOUPLERS OPTOELECTRONICS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTLto ORDER INFORMATION LOGIC COMPATIBILITY PART NUMBER INPUT OUTPUT TTL 740L6000 LSTTL TTL 740L6001 LSTTL CMOS 740L6010 LSTTL CMOS 740L6011 LSTTL	OCR Scan	740L6000 740L6001 740L6010 740L6011 740L6011 transistor c2026 c2026 c2026 transistor data transistor equivalent c2026 C2026 TRANSISTOR c2037	PDF
Untitled Abstract: No abstract text available Text: O SYNERGY SEMICONDUCTOR 3.3V SINGLE SUPPLY OCTAL PECL/TTL-TO-TTL PECL/TTL-to-TTL version of popular ECLinPS E111AE/LE Guaranteed low skew specification Three-state enable Differential internal design V bb output for single-ended operation Extra TTL and ECL power/ground pins	OCR Scan	E111AE/LE SY100H646L 28-lead H646L HA643	PDF
transistor c2026 Abstract: c2026 transistor data 740L6000 c2028 transistor data C2036 c2026 transistor equivalent c2026 C2037 transistor C2003 740L6000 equivalent Text: eu HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS OPTOELECTRONICS OPTO/LOGIC TTL BUFFER TTLINVERTER CMOS BUFFER CMOS INVERTER LSTTL to \ TM ORDER INFORMATION LOGIC COMPATIBILITY PART NUMBER INPUT OUTPUT 740L6000 LSTTL TTL TTL 740L6001 LSTTL 740L6010 LSTTL CMOS 740L6011 LSTTL	OCR Scan	740L6000 740L6001 740L6010 740L6011 740L6011 transistor c2026 c2026 transistor data c2028 transistor data C2036 c2026 transistor equivalent c2026 C2037 transistor C2003 740L6000 equivalent	PDF
Untitled Abstract: No abstract text available Text: ^ LOW POWER HEX TTL-tO-ECL TRANSLATOR SYNERGY SY100S324 SEMICONDUCTOR DESCRIPTION FEATURES The SY100S324 is a hex translator designed to convert TTL logic levels to 100K ECL levels. The inputs are TTL compatible with differential outputs that can either be used	OCR Scan	SY100S324 SY100S324 SY100S324DC D24-1 SY100S324FC F24-1 SY100S324JC J28-1	PDF
PDU-1316-20 Abstract: PDU-1316-1 PDU-1316-12 PDU-1316-2 PDU-1316-5 PDU-1316-100 NS225 Text: data \flaa Digitally Programmable delay \ë SERIES: PDU-1316 De ay Units deviceli«:. 4-Bit TTL Interfaced Specifications: Test Conditions: • Input signal requirement: TTL logic ■ Output fan-out: TTL schottky load ■ Delay variation: Monotonic in one direction	OCR Scan	pdu-i316 PDU-1316-1 PDU-1316-2 PDU-1316-3 PDU-1316-4 PDU-1316-5 PDU-1316-6 PDU-1316-8 PDU-1316-10 PDU-1316-20 PDU-1316-12 PDU-1316-100 NS225	PDF
Untitled Abstract: No abstract text available Text: * SYNERGY LOW-POWER HEX TTL-TO-PECL TRANSLATOR SY100S391 SEMICONDUCTOR DESCRIPTION FEATURES Operates from a single +5V supply Differential PECL outputs The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique	OCR Scan	SY100S391 SY100S391	PDF
Untitled Abstract: No abstract text available Text: * LOW POWER HEX TTL-to-ECL TRANSLATOR SYNERGY SY100S324 SEMICONDUCTOR FEATURES DESCRIPTION The SY100S324 is a hex translator designed to convert TTL logic levels to 100K ECL levels. The inputs are TTL compatible with differential outputs that can either be	OCR Scan	SY100S324 SY100S324 SY100S324DC D24-1 SY100S324FC F24-1 100S324JC J28-1 SY100S324JCTR	PDF

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TTL LOGIC Search Results

TTL LOGIC Result Highlights (5)

TTL LOGIC Datasheets Context Search

Untitled

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IDT74GTLP816

MSI Logic

IC TTL 74LS00

CY101E383

2n2222 fairchild

ttlpd

HLT28

HLT28

F100K

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GTLP8T306

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GTLP16612

100324PC

740L6000

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transistor c2026

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PDU-1316-20

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