ICD2062A
Abstract: ICD2062B
Text: ICD2062B Dual Programmable ECL/TTL Clock Generator to produce the following: a 10 K compatible complementary ECL output signal for highĆspeed video RAMDACs, a highĆspeed TTL output signal for video RAMs and system logic operation, and the requisite load, control, and clock
|
Original
|
ICD2062B
165MHz
ICD2062B
ICD2062A
|
PDF
|
crt monitor circuit diagram
Abstract: 8-bit VGA ramdac ICD2062B icd2062 185-000 HSYNC, VSYNC input output ICD2062A
Text: fax id: 3502 1I CD20 62B ICD2062B Dual Programmable ECL/TTL Clock Generator Features • Second generation dual oscillator graphics clock generator • PECL Video Outputs: 508 kHz to 165 MHz • TTL Outputs: 508 kHz to 120 MHz • Individually programmable PLLs using a highly reliable, Manchester-encoded, 21-bit serial data word
|
Original
|
ICD2062B
21-bit
crt monitor circuit diagram
8-bit VGA ramdac
ICD2062B
icd2062
185-000
HSYNC, VSYNC input output
ICD2062A
|
PDF
|
award Flash BIOS
Abstract: R5C485 VT1612A Realtek 8100BL R5C4 VT82C686B TTL to vga flash disk pcmcia 8mb R5C485II TM5800
Text: EmCORE-t6032 Transmeta Crusoe 800MHz 3.5" Miniboard with VGA/LCD, LAN, USB, PCMCIA PCMCIA 2.5” HDD Holder Features ✱ Transmeta Crusoe 800 MHz Fanless LPT ✱ DDR SDRAM up to 512MB (SODIMM 200pin) ✱ SMI722G8 3D Video Controller with TTL and CRT support
|
Original
|
EmCORE-t6032
800MHz
512MB
200pin)
SMI722G8
10/100Mbps
8100BL
TM5800
800MHz
512MB
award Flash BIOS
R5C485
VT1612A
Realtek 8100BL
R5C4
VT82C686B
TTL to vga
flash disk pcmcia 8mb
R5C485II
|
PDF
|
Untitled
Abstract: No abstract text available
Text: THC63LVD103D _Rev.3.0_E THC63LVD103D 160MHz 30Bits COLOR LVDS Transmitter General Description Features The THC63LVD103D transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to 1080p 60Hz . The THC63LVD103D converts 35bits of CMOS/TTL
|
Original
|
THC63LVD103D
160MHz
30Bits
THC63LVD103D
1080p
35bits
160MHz,
|
PDF
|
THC63LVD103D
Abstract: THC63LVD103 thine electronic
Text: THC63LVD103D _Rev.1.0_E1 THC63LVD103D 135MHz 30Bits COLOR LVDS Transmitter General Description Features The THC63LVD103D transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA+ resolutions. The THC63LVD103D converts 35bits of CMOS/TTL
|
Original
|
THC63LVD103D
135MHz
30Bits
THC63LVD103D
35bits
135MHz,
945Mbps
THC63LVD103
thine electronic
|
PDF
|
THC63LVD103
Abstract: thine electronic LVDS Transmitter THine te1819 THC63LVDM63R M83R 30Bits
Text: THC63LVD103 _Rev2.2 THC63LVD103 135MHz 30Bits COLOR LVDS Transmitter General Description Features The THC63LVD103 transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA+ resolutions. The THC63LVD103 converts 35bits of CMOS/TTL
|
Original
|
THC63LVD103
135MHz
30Bits
THC63LVD103
35bits
135MHz,
945Mbps
thine electronic
LVDS Transmitter THine
te1819
THC63LVDM63R
M83R
|
PDF
|
thine electronic
Abstract: THC63LVD103 THC63LVDM63R LVDS Transmitter THine
Text: THC63LVD103 _Rev2.1 THC63LVD103 135MHz 30Bits COLOR LVDS Transmitter General Description Features The THC63LVD103 transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA+ resolutions. The THC63LVD103 converts 35bits of CMOS/TTL
|
Original
|
THC63LVD103
135MHz
30Bits
THC63LVD103
35bits
135MHz,
945Mbps
thine electronic
THC63LVDM63R
LVDS Transmitter THine
|
PDF
|
THC63LVD103D
Abstract: THV63LVD103D TTL display 7 THC63LVD103 lvds cable
Text: THC63LVD103D _Rev.1.10_E THC63LVD103D 135MHz 30Bits COLOR LVDS Transmitter General Description Features The THC63LVD103D transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA+ resolutions. The THC63LVD103D converts 35bits of CMOS/TTL
|
Original
|
THC63LVD103D
135MHz
30Bits
THC63LVD103D
35bits
135MHz,
945Mbps
THV63LVD103D
TTL display 7
THC63LVD103
lvds cable
|
PDF
|
TTL to vga
Abstract: LVDS 30 pin to vga LVDS to vga TTL parallel to vga LVDS display 30 pin 30pin vga header Digital Displays SFD064VX1ADV PD050VX2 of 30 pin LVDS
Text: 1.17.06 TECHNICAL BRIEF BY: AZD ENGINEERING TFT Digital Board Signals AZ Displays offers decoder boards suitable to display full motion video on its digital TFT panels. Digital displays are designed to interface to a digital-to-analog board via TTL transistor to transistor logic or LVDS (low voltage differential signal).
|
Original
|
30-pin
12-pin
PD050VX2
SFD064VX1ADV/VGA/INVT
TTL to vga
LVDS 30 pin to vga
LVDS to vga
TTL parallel to vga
LVDS display 30 pin
30pin vga header
Digital Displays
SFD064VX1ADV
of 30 pin LVDS
|
PDF
|
HIP6020A
Abstract: 593D HIP6020ACB TB363 TB379
Text: HIP6020A TM Data Sheet September 2001 Advanced Dual PWM and Dual Linear Power Controller The HIP6020A includes an Intel-compatible, TTL 5-input digital-to-analog converter DAC that adjusts the core PWM output voltage from 1.3VDC to 2.05VDC in 0.05V steps and
|
Original
|
HIP6020A
HIP6020A
28-pin
CH-1009
593D
HIP6020ACB
TB363
TB379
|
PDF
|
HIP6020A
Abstract: 593D HIP6020ACB TB363 TB379
Text: HIP6020A TM Data Sheet November 2000 Advanced Dual PWM and Dual Linear Power Controller The HIP6020A includes an Intel-compatible, TTL 5-input digital-to-analog converter DAC that adjusts the core PWM output voltage from 1.3VDC to 2.05VDC in 0.05V steps and
|
Original
|
HIP6020A
HIP6020A
28-pin
593D
HIP6020ACB
TB363
TB379
|
PDF
|
VG-660
Abstract: VG660 VG365 80188 PIN DIAGRAM OF 80186 Vadem vg660 80186 CPU subsystem VG469 VG-468 80c188 application note
Text: SUPPORT COMPONENTS NATIONAL SEMICONDUCTOR CGS253x Quad 1 to 4 Clock Drivers • ■ ■ ■ ■ ■ ■ ■ ■ Pin-to-Pin Skew of Less Than 350 ps Part-to-Part Skew of Less Than 650 ps Output Series Resistor Integrated Into CGS2537 Supports TTL and CMOS Output
|
Original
|
CGS253x
CGS2537
Intel386TM
Intel486TM
VG-660
VG660
VG365
80188
PIN DIAGRAM OF 80186
Vadem vg660
80186 CPU subsystem
VG469
VG-468
80c188 application note
|
PDF
|
c3199
Abstract: transistor c3199 C3199 equivalent cmps 10 C3199 transistor AD725 vga to s-video ic TTL RGB to analog RGB SONY PVM VGA to NTSC
Text: a Low Cost RGB to NTSC/PAL Encoder with Luma Trap Port AD725 FEATURES Composite Video Output: Both NTSC and PAL Chrominance and Luminance S-Video Outputs Luma Trap Port to Eliminate Cross Color Artifacts TTL Logic Levels Integrated Delay Line and Auto-Tuned Filters
|
Original
|
AD725
AD725
AD725.
16-Lead
C3199
transistor c3199
C3199 equivalent
cmps 10
C3199 transistor
vga to s-video ic
TTL RGB to analog RGB
SONY PVM
VGA to NTSC
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Low Cost RGB to NTSC/PAL Encoder with Luma Trap Port AD725 a FEATURES Composite Video Output: Both NTSC and PAL Chrominance and Luminance S-Video Outputs Luma Trap Port to Eliminate Cross Color Artifacts TTL Logic Levels Integrated Delay Line and Auto-Tuned Filters
|
Original
|
AD725
C3199â
|
PDF
|
|
|
C3199 equivalent
Abstract: c3199 cmps 10 circuit diagram SHARP TV Model 21A PVM-1354Q SONY PVM 1354q C3199 y vga to s-video ic Block Diagram of PAL D TV receiver AD725
Text: BACK a Low Cost RGB to NTSC/PAL Encoder with Luma Trap Port AD725 FEATURES Composite Video Output: Both NTSC and PAL Chrominance and Luminance S-Video Outputs Luma Trap Port to Eliminate Cross Color Artifacts TTL Logic Levels Integrated Delay Line and Auto-Tuned Filters
|
Original
|
AD725
AD725
16-Lead
C3199
C3199 equivalent
cmps 10
circuit diagram SHARP TV Model 21A
PVM-1354Q
SONY PVM 1354q
C3199 y
vga to s-video ic
Block Diagram of PAL D TV receiver
|
PDF
|
lvds 20 pin to 30 pin
Abstract: THC63LVDF84 TISN65LVDS94 tssop-56pin LVDS 31 pin thine ordering information
Text: Integrated Circuit Systems V386 8-bit LVDS Video Receiver Feature list • Converts 4-pair of LVDS data streams back into parallel 28 bits bits of CMOS/TTL data • Up to 2.38 Gbps throughput or 297.5Mbytes/sec bandwidth • Wide clock frequency range from 20MHz to
|
Original
|
20MHz
85MHz
350mV
V386GLF
V386GLFTR
lvds 20 pin to 30 pin
THC63LVDF84
TISN65LVDS94
tssop-56pin
LVDS 31 pin
thine ordering information
|
PDF
|
VIA Mark CoreFusion 533MHz processor
Abstract: VIA Mark CoreFusion pc133 sdram 512 COREFUSION 800 PCA-67753F-Q0A1E LVDS bridge 18bit gold finger RTL8100C lcd LVDS 40pin to 50pin adapter CoreFusion 533MHz
Text: PCA-6775 VIA ISA Half-sized SBC, with VGA/LVDS/TTL/LAN/SSD/USB 2.0 Features • VIA Mark 533/800 MHz CPU • 128 MB Memory on board, support 1 SODIMM socket SDRAM up to 512 MB 10/100 Base-T Ethernet Low power consumption and fanless RoHS COMPLIANT
|
Original
|
PCA-6775
2002/95/EC
16-bit/
PC133
144-pin
V701140201
RS-232/422/485)
PCA-6775F-L0A1E
PCA-6775F-Q0A1E
IPC-644BP-15ZE
VIA Mark CoreFusion 533MHz processor
VIA Mark CoreFusion
pc133 sdram 512
COREFUSION 800
PCA-67753F-Q0A1E
LVDS bridge 18bit
gold finger
RTL8100C
lcd LVDS 40pin to 50pin adapter
CoreFusion 533MHz
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 100325 £3 National ÆÆ Semiconductor 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each cir cuit to be used as an inverting, non-inverting or differential
|
OCR Scan
|
F100K
|
PDF
|
ICD2062A
Abstract: ICD2062B bt ramdac ICD2062-BSC-2
Text: fax id: 3502 ICD2062B Dual Programmable ECL/TTL Clock Generator Features • Second generation dual oscillator graphics clock gen erator • PECL Video Outputs: 508 kHz to 165 MHz • TTL Outputs: 508 kHz to 120 MHz • Individually programmable PLLs using a highly reli
|
OCR Scan
|
ICD2062B
21-bit
ICD2062A
ICD2062B
bt ramdac
ICD2062-BSC-2
|
PDF
|
VCLK generator ttl
Abstract: ICD2062A ICD2062B 16 channel demux ICD2062BSC-2 Q0011 LIS 8514
Text: fax id: 3502 ICD2062B Dual Programmable ECL/TTL Clock Generator Features • Second generation dual oscillator graphics clock gen erator • PECL Video Outputs: 508 kHz to 165 MHz • TTL Outputs: 508 kHz to 120 MHz • Individually programmable PLLs using a highly reli
|
OCR Scan
|
ICD2062B
21-bit
VCLK generator ttl
ICD2062A
ICD2062B
16 channel demux
ICD2062BSC-2
Q0011
LIS 8514
|
PDF
|
F100325
Abstract: F100125 F100K
Text: 100125 5251 N a tio n a l w im S e m ic o n d u c to r F100125 Hex ECL-to-TTL Translator General Description The F100125 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each cir cuit to be used as an inverting, non-inverting or differential
|
OCR Scan
|
F100125
F100125
F100K
tl/f/9849-5
500il
tl/f/9849-6
F100325
|
PDF
|
operation of solenoid valve using 555 timer ic
Abstract: driver IC for IRF540 MOSFET
Text: General Description Features 2.75V to 30V operation 1OOjaA maximum supply current 5V supply 15 jaA typical off-state current Internal charge pump TTL compatible input Withstands 60V transient (load dump) Reverse battery protected to - 2 0 V Inductive spike protected to - 2 0 V
|
OCR Scan
|
MIC5016
MIC5017
MIC5016/7
16-Pin
18-Pin
operation of solenoid valve using 555 timer ic
driver IC for IRF540 MOSFET
|
PDF
|
QFP100
Abstract: QFP52 TDA8752
Text: Philips Semiconductors Objective specification Triple high speed Analog-to-Digital Converter ADC TDA8752 FEATURES Triple 8-bit ADC Sampling rate up to 80 MHz BUS 1C controllable via a serial interface, which can be either l2C-bus or 3-wire, selected via a TTL input pin
|
OCR Scan
|
|
PDF
|
QFP100
Abstract: QFP52 TDA8752 TDA8752H/laf 0001 analog
Text: Philips Semiconductors Preliminary specification Triple high speed Analog-to-Digital Converter ADC TDA8752 FEATURES Triple 8-bit ADC Sampling rate up to 80 MHz BUS 1C controllable via a serial interface, which can be either l2C-bus or 3-wire, selected via a TTL input pin
|
OCR Scan
|
|
PDF
|
