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    ULTRA37256V Search Results

    ULTRA37256V Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    Ultra37256V Cypress Semiconductor UltraLogic High-Performance CPLDs Original PDF
    Ultra37256V Cypress Semiconductor An Introduction to In-System Reprogramming (ISR) with the Ultra37000 Original PDF
    Ultra37256V Cypress Semiconductor UltraLogic 256-Macrocell 3.3V ISR CPLD Scan PDF

    ULTRA37256V Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    O96-I

    Abstract: No abstract text available
    Text: fax id: 6149 1Ult ra372 56 V PRELIMINARY Ultra37256V UltraLogic 256-Macrocell 3.3V ISR™ CPLD • Up to 192 I/Os — plus 5 dedicated inputs including 4 clock inputs • Product-term clocking • IEEE1149.1 JTAG boundary scan • Programmable slew rate control on individual I/Os


    Original     		PDF ra372 Ultra37256V 256-Macrocell IEEE1149 160-pin 208-pin 256-lead Ultra37000 O96-I

    CY37256VP160-100AC

    Abstract: h jtag
    Text: fax id: 6149 PRELIMINARY Ultra37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 10 ns Features — tS = 5.5 ns • 256 macrocells in sixteen logic blocks • IEEE standard 3.3V operation — 3.3V ISR — tCO = 6.5 ns Product-term clocking IEEE1149.1 JTAG boundary scan


    Original     		PDF Ultra37256V 256-Macrocell IEEE1149 160-pin 208-pin 256-lead Ultra37192V Ultra37128V CY37256VP160-100AC h jtag

    tlp 453

    Abstract: No abstract text available
    Text: fax id: 6151 PRELIMINARY Ultra37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 10 ns Features — tS = 5.5 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — 3.3V ISR • • • • • • • • • — 5V tolerant


    Original     		PDF Ultra37192V 192-Macrocell IEEE1149 tlp 453

    CY3120

    Abstract: CY3620 CY3620R62 delta39k
    Text: CY3620 WarpISR Design Kit for CPLDs Features • Complete design and programming kit for In-System Reprogrammable™ ISR™ CPLDs • Industry-leading Warp design software for VHDL and Verilog • Easy-to-use ISR PC programmer for on-board programming


    Original     		PDF CY3620 Delta39KTM, Ultra37000TM Delta39K FLASH370iTM CY3600i Delta39K\Ultra37000 CY3620 Quantum38K CY3120 CY3620R62

    CY3120

    Abstract: CY3620 CY3620R62 Ultra37000TM ultraISR CABLE
    Text: y 9, 3610 CY3620 WarpISR Design Kit for CPLDs Features • Complete design and programming kit for In-System Reprogrammable™ ISR™ CPLDs • Industry-leading Warp design software for VHDL and Verilog • Easy-to-use ISR PC programmer for on-board


    Original     		PDF CY3620 Delta39KTM, Quantum38KTM, Ultra37000TM Delta39K" FLASH370iTM CY3600i Delta39KTM\Ultra37000TM CY3620 CY3120 CY3620R62 ultraISR CABLE

    CY3120

    Abstract: CY3620 CY3620R62 Ultra37000TM
    Text: 13, 3610 CY3620 WarpISR Design Kit for CPLDs Features • Complete design and programming kit for In-System Reprogrammable™ ISR™ CPLDs • Industry-leading Warp design software for VHDL and Verilog • Easy-to-use ISR PC programmer for on-board


    Original     		PDF CY3620 Delta39KTM, Quantum38KTM, Ultra37000TM Delta39K" FLASH370iTM CY3600i Delta39KTM\Ultra37000TM CY3620 CY3120 CY3620R62

    208-Pin PQFP

    Abstract: CY3120 CY3620 CY3620R62 delta39k cable running sheet
    Text: CY3620 WarpISR Design Kit for CPLDs Features • Complete design and programming kit for In-System Reprogrammable™ ISR™ CPLDs • Industry-leading Warp design software for VHDL and Verilog • Easy-to-use ISR PC programmer for on-board programming


    Original     		PDF CY3620 Delta39KTM, Ultra37000TM Delta39K FLASH370iTM CY3600i Delta39K\Ultra37000 CY3620 Quantum38K 208-Pin PQFP CY3120 CY3620R62 cable running sheet

    Untitled

    Abstract: No abstract text available
    Text: fax id: 6149 W CYPRESS Ultra37256V PRELIMINARY UltraLogic TM 256-Macrocell 3.3V ISR CPLD • Up to 192 1/Os — plus 5 dedicated inputs including 4 clock inputs Features • 256 macrocells in sixteen logic blocks • IEEE standard 3.3V operation — 3.3V ISR


    OCR Scan     		PDF Ultra37256V 256-Macrocell IEEE1149 160-pin 208-pin 256-lead Ultra37000

    T1119

    Abstract: No abstract text available
    Text: ^^W ^C Y P R K S S Ultra37256V preliminary UltraLogic 3.3V 256-Macrocell ISR™ CPLD Features — t PD = 12 ns — ts = 7 ns • 256 m a cro c ells in sixteen log ic blocks — t co = 6.5 ns • 3.3 V In -S ystem R ep ro g ram m ab le™ IS R ™ • P ro d uct-term clo ckin g


    OCR Scan     		PDF IEEE1149 Ultra37256V 256-Macrocell T1119

    Untitled

    Abstract: No abstract text available
    Text: fax id: 6149 CYPRESS UltraLogic 3.3V 256-Macrocell ISR™ CPLD PRELIMINARY Ultra37256V — t PD = 12 ns Features — ts = 6 ns • 256 macrocells in sixteen logic blocks • IEEE standard 3.3V operation — tco = 7 ns — 3.3V ISR — 5V tolerant • 3.3V In-System Reprogram mable ISR™


    OCR Scan     		PDF 256-Macrocell Ultra37256V IEEE1149

    11J2

    Abstract: No abstract text available
    Text: . : f j .T-iT-r-r-PRELIMINARY Y Ultra37256V - H UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 ns • 256 macrocells in sixteen logic blocks — tc o = 6.5 ns • 3.3V In-System Reprogrammable™ ISR™


    OCR Scan     		PDF Ultra37256V 256-Macrocell IEEE1149 11J2

    CY3600

    Abstract: No abstract text available
    Text: fax id: 6149 SS i^K JS f r i s a l i i J F ; U FTV fST “ ¿ N &*• I F l m c b PRELIMINARY Ultra37256V t i UltraLogic 256-Macrocell 3.3V ISR™ CPLD Features • Up to 192 1/Os — plus 5 d ed icated inp u ts including 4 clo ck inputs • 256 m a cro c ells in six te en logic blocks


    OCR Scan     		PDF Ultra37256V 256-Macrocell IEEE1149 CY3600

    Untitled

    Abstract: No abstract text available
    Text: . _ n « PRELIMINARY Ultra37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns • • • • • • — JTAG-compliant on-board programming


    OCR Scan     		PDF Ultra37256V 256-Macrocell 160-pin 208-pin 256-lead Ultra37256, Itra37128/37128V, Itra37192/37192V, Itra37384/37384V, Itra37512/37512V

    Untitled

    Abstract: No abstract text available
    Text: fax id: 6149 W CYPRESS Ultra37256V PRELIMINARY UltraLogic TM 256-Macrocell 3.3V ISR CPLD • Up to 192 1/Os — plus 5 dedicated inputs including 4 clock inputs Features • 256 macrocells in sixteen logic blocks • IEEE standard 3.3V operation — 3.3V ISR


    OCR Scan     		PDF Ultra37256V 256-Macrocell IEEE1149 160-pin 208-pin 256-lead Ultra37000

    Untitled

    Abstract: No abstract text available
    Text: • ■ J ^ m n r n n PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 256 macrocells in sixteen logic blocks • In-System Reprogram mable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes


    OCR Scan     		PDF Ultra37256 256-Macrocell IEEE1149

    O16I

    Abstract: 7256P 99L0
    Text: PREUM INAm Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os Low power option on individual logic block basis 5V and 3.3V I/O capability


    OCR Scan     		PDF Ultra37256 256-Macrocell IEEE1149 160-pin 208-pin 256-lead O16I 7256P 99L0

    5V19

    Abstract: No abstract text available
    Text: fax id: 6149 UltraLogic 256-Macrocell 3.3V ISR™ CPLD Up to 192 l/Os Feat u res — plus 5 dedicated inputs including 4 clock inputs • 256 macrocel l s in sixteen logic blocks Product - t erm clocking • I EEE standard 3.3V operation I EE E1149.1 JTAG boundary scan


    OCR Scan     		PDF 256-Macrocell E1149 5V19

    Untitled

    Abstract: No abstract text available
    Text: fax id: 6151 CYPRESS UltraLogic 3.3V 192-Macrocell ISR™ CPLD PRELIMINARY Ultra37192V — t PD = 12 ns Features — ts = 6 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 7 ns Product-term clocking IEEE1149.1 JTAG boundary scan


    OCR Scan     		PDF 192-Macrocell Ultra37192V IEEE1149 160-pin