Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    UNIVERSAL SHIFT REGISTER USING CPLD Search Results

    UNIVERSAL SHIFT REGISTER USING CPLD Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    54194W Rochester Electronics LLC 54194 - 4-Bit BiDirectional Universal Shift Reg Visit Rochester Electronics LLC Buy
    SF-10GSFPPLCL-000 Amphenol Cables on Demand Amphenol SF-10GSFPPLCL-000 SFP+ Optical Module - 10GBASE-SR (up to 300m/984') SFP+ Multimode Optical Transceiver Module (Duplex LC Connectors) - Cisco & HP Compatible Datasheet
    SF-XP85B102DX-000 Amphenol Cables on Demand Amphenol SF-XP85B102DX-000 SFP28 25GBASE-SR Short-Range 850nm Multi-Mode Optical Transceiver Module (Duplex LC Connector) by Amphenol XGIGA [XP85B102DX] Datasheet
    SF-QXP85B402D-000 Amphenol Cables on Demand Amphenol SF-QXP85B402D-000 QSFP28 100GBASE-SR Short-Range 850nm Multi-Mode Optical Transceiver Module (MTP/MPO Connector) by Amphenol XGIGA [QXP85B402D] Datasheet
    CS-USB3.1TYPC-001M Amphenol Cables on Demand Amphenol CS-USB3.1TYPC-001M Amphenol Premium USB 3.1 Gen2 Certified USB Type A-C Cable - USB 3.0 Type A Male to Type C Male [10.0 Gbps SuperSpeed] 1m (3.3ft) Datasheet

    UNIVERSAL SHIFT REGISTER USING CPLD Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: R CoolRunner XPLA3 CPLD DS012 v1.6 January 6, 2003 14 Preliminary Product Specification Features • • • • • • • • • • • • • • • • • • Fast Zero Power (FZP) design technique provides ultra-low power and very high speed


    Original     		PDF DS012 devices--10 XC9500XL XCR3384XL TQ144

    Untitled

    Abstract: No abstract text available
    Text: R CoolRunner XPLA3 CPLD DS012 v1.5 January 7, 2002 14 Features • • • • • • • • Advance Product Specification • Fast Zero Power (FZP) design technique provides ultra-low power and very high speed Innovative XPLA3 architecture combines high speed


    Original     		PDF DS012 XCR3512XL 324-pin devices--10

    schematic diagram UPS 600 Power structure

    Abstract: AS 108-120 DS012 MC16 PT16 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL
    Text: R CoolRunner XPLA3 CPLD DS012 v1.4 April 11, 2001 14 Features • • • • • • • • Fast Zero Power (FZP ) design technique provides ultra-low power and very high speed Innovative XPLA3 architecture combines high speed with extreme flexibility


    Original     		PDF DS012 XCR3512XL 324-pin devices--10 schematic diagram UPS 600 Power structure AS 108-120 DS012 MC16 PT16 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL

    universal shift register using cpld

    Abstract: mc16 DS012 PT16 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL 280-Pin
    Text: R CoolRunner XPLA3 CPLD DS012 v1.3 February 9, 2001 14 Features • • • • • • • • Fast Zero Power (FZP ) design technique provides ultra-low power and very high speed Innovative XPLA3 architecture combines high speed with extreme flexibility


    Original     		PDF DS012 universal shift register using cpld mc16 DS012 PT16 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL 280-Pin

    XCR3256xl 144

    Abstract: AS 108-120 DS012 MC16 PT16 TQ144 XCR3032XL XCR3064XL XCR3128XL XCR3256XL
    Text: R CoolRunner XPLA3 CPLD DS012 v1.7 June 23, 2003 14 Preliminary Product Specification Features • • • • • • • • • • • • • • • • • • Fast Zero Power (FZP) design technique provides ultra-low power and very high speed


    Original     		PDF DS012 XC9500XL XCR3384XL TQ144 XCR3256xl 144 AS 108-120 DS012 MC16 PT16 XCR3032XL XCR3064XL XCR3128XL XCR3256XL

    CoolRunner XPLA3 CPLD Family

    Abstract: AS 108-120 DS012 MC16 PT16 TQ144 XCR3032XL XCR3064XL XCR3128XL XCR3256XL
    Text: R CoolRunner XPLA3 CPLD DS012 v2.4 September 8, 2008 Product Specification 14 Features • • • • • • • • Fast Zero Power (FZP) design technique provides ultra-low power and very high speed - Typical Standby Current of 17 to 18 A at 25°C


    Original     		PDF DS012 asynch3/04 PCG44 xcn07022 CoolRunner XPLA3 CPLD Family AS 108-120 DS012 MC16 PT16 TQ144 XCR3032XL XCR3064XL XCR3128XL XCR3256XL

    CoolRunner XPLA3 CPLD Family

    Abstract: DS012 MC16 PT16 TQ144 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL
    Text: CoolRunner XPLA3 CPLD R DS012 v2.2 March 31, 2006 14 Features • • • • • • • Product Specification • Fast Zero Power (FZP) design technique provides ultra-low power and very high speed - Typical Standby Current of 17 to 18 A at 25° C


    Original     		PDF DS012 asynch500XL XCR3384XL TQ144 CoolRunner XPLA3 CPLD Family DS012 MC16 PT16 XCR3032XL XCR3064XL XCR3128XL XCR3256XL

    DS012

    Abstract: MC16 PT16 TQ144 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL XCR3512XL
    Text: R CoolRunner XPLA3 CPLD DS012 v1.8 February 13, 2004 14 Features • • • • • • • • Preliminary Product Specification • Fast Zero Power (FZP) design technique provides ultra-low power and very high speed Innovative XPLA3 architecture combines high speed


    Original     		PDF DS012 XC9500XL XCR3384XL TQ144 DS012 MC16 PT16 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3512XL

    Untitled

    Abstract: No abstract text available
    Text: R CoolRunner XPLA3 CPLD DS012 v2.0 January 10, 2005 14 Features • • • • • • • • Preliminary Product Specification • Fast Zero Power (FZP) design technique provides ultra-low power and very high speed Innovative XPLA3 architecture combines high speed


    Original     		PDF DS012 XC9500XL XCR3384XL TQ144

    AS 108-120

    Abstract: DS012 MC16 PT16 TQ144 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL
    Text: R CoolRunner XPLA3 CPLD DS012 v1.9 September 29, 2004 14 Features • • • • • • • • Preliminary Product Specification • Fast Zero Power (FZP) design technique provides ultra-low power and very high speed Innovative XPLA3 architecture combines high speed


    Original     		PDF DS012 XC9500XL XCR3384XL TQ144 AS 108-120 DS012 MC16 PT16 XCR3032XL XCR3064XL XCR3128XL XCR3256XL

    Untitled

    Abstract: No abstract text available
    Text: R CoolRunner XPLA3 CPLD DS012 v2.1 April 8, 2005 14 Features • • • • • • • Product Specification • Fast Zero Power (FZP) design technique provides ultra-low power and very high speed - Typical Standby Current of 17 to 18 µA at 25° C


    Original     		PDF DS012 XC9500XL XCR3384XL TQ144

    DS012

    Abstract: MC15 PT16 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL
    Text: APPLICATION NOTE  DS012 v1.0 January 20, 2000 CoolRunner XPLA3 CPLD 14* Advance Product Specification Features Family Overview • The CoolRunner XPLA3 (eXtended Programmable Logic Array) family of CPLDs is targeted for low power systems that include portable, handheld, and power sensitive applications. Each member of the XPLA3 family includes Fast


    Original     		PDF DS012 CS280 PQ208 TQ144 CS144 VQ100 XCR3032XL XCR3064XL XCR3128XL XCR3256XL DS012 MC15 PT16 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL

    DS012

    Abstract: MC15 PT16 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL
    Text: APPLICATION NOTE  DS012 v1.1 March 3, 2000 CoolRunner XPLA3 CPLD 14* Advance Product Specification Features Family Overview • The CoolRunner XPLA3 (eXtended Programmable Logic Array) family of CPLDs is targeted for low power systems that include portable, handheld, and power sensitive applications. Each member of the XPLA3 family includes Fast


    Original     		PDF DS012 CS280 PQ208 TQ144 CS144 VQ100 XCR3032XL XCR3064XL XCR3128XL XCR3256XL DS012 MC15 PT16 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL

    CMOS 0.8mm process cross

    Abstract: XCN07022 CoolRunner XPLA3 CPLD Family XCR3256XL XCR3384XL XCR3512XL DS012 MC16 TQ144 XCR3032XL
    Text: R CoolRunner XPLA3 CPLD DS012 v2.5 May 26, 2009 Product Specification 14 Features • • Fast Zero Power (FZP) design technique provides ultra-low power and very high speed - Typical Standby Current of 17 to 18 A at 25°C Innovative CoolRunner XPLA3 architecture


    Original     		PDF DS012 CMOS 0.8mm process cross XCN07022 CoolRunner XPLA3 CPLD Family XCR3256XL XCR3384XL XCR3512XL DS012 MC16 TQ144 XCR3032XL

    block diagram UART using VHDL

    Abstract: M16550A uart verilog testbench
    Text: Serial Communications FPGA/CPLD IP Inventra M16550A-B1 UART with FIFOs D A T A S H E E T CLK RCLK RCLK_BAUD BAUD RATE GENERATOR BAUD M16550A key features: • Software compatible with the BRGE NSC NS16550A DI[7:0] DA[7:0] • Programmable word length, stop bits


    Original     		PDF M16550A-B1 M16550A NS16550A 16-byte Delta39KTM CY39100V676-200MBC 47MHz PD-40127 block diagram UART using VHDL uart verilog testbench

    vhdl code for rs232 receiver

    Abstract: verilog code for uart communication vhdl code for uart communication xilinx uart verilog code uart verilog code verilog code for serial transmitter vhdl code for serial transmitter interface of rs232 to UART in VHDL UART using VHDL 16 bit register vhdl
    Text: Application Note: CPLD R UARTs in Xilinx CPLDs XAPP341 v1.2 November 28, 2000 Summary This application note provides a functional description of VHDL and Verilog source code for a UART. The code is used to target the XC95144 and XCR3128XL CPLDs. The functionality of


    Original     		PDF XAPP341 XC95144 XCR3128XL RS232. XAPP341 XCR3128 vhdl code for rs232 receiver verilog code for uart communication vhdl code for uart communication xilinx uart verilog code uart verilog code verilog code for serial transmitter vhdl code for serial transmitter interface of rs232 to UART in VHDL UART using VHDL 16 bit register vhdl

    xilinx uart verilog code

    Abstract: vhdl code for rs232 receiver vhdl code for uart communication vhdl code for shift register vhdl code for serial transmitter 16 bit register vhdl vhdl code for rs232 interface UART using VHDL uart verilog code vhdl code for 8 bit shift register
    Text: Application Note: CPLD R UARTs in Xilinx CPLDs XAPP341 v1.1 April 17, 2000 Summary This application note provides a functional description of VHDL and Verilog source code for a UART. The code is used to target the XC95144 and XCR3128 CPLDs. The functionality of the


    Original     		PDF XAPP341 XC95144 XCR3128 RS232. XAPP341 xilinx uart verilog code vhdl code for rs232 receiver vhdl code for uart communication vhdl code for shift register vhdl code for serial transmitter 16 bit register vhdl vhdl code for rs232 interface UART using VHDL uart verilog code vhdl code for 8 bit shift register

    alarm clock design of digital VHDL

    Abstract: digital dice design of digital VHDL altera alarm clock design of digital VHDL altera FPT-XCS10TQ144 design counter traffic light different vendors of cpld and fpga digital dice design VHDL traffic light using VHDL FPT1 xcs10tq144
    Text: FPT-1 CPLD/FPGA Logical Circuit Design Experimental Board Test Content ! Combined logic design, simulation and test: 1. Basic logic 2. Deducter 3. Decoder 4. Combined logic 5. Comparator 6. Multiplexer 7. Adder 8. Compiler 9. Demultiplexer ! Sequential logic circuit design simulaBrief Introduction


    Original     		PDF 25pin alarm clock design of digital VHDL digital dice design of digital VHDL altera alarm clock design of digital VHDL altera FPT-XCS10TQ144 design counter traffic light different vendors of cpld and fpga digital dice design VHDL traffic light using VHDL FPT1 xcs10tq144

    vhdl code for rs232 receiver

    Abstract: xilinx uart verilog code interface of rs232 to UART in VHDL vhdl code for uart communication vhdl code for serial transmitter vhdl code 16 bit microprocessor uart verilog code verilog code for serial transmitter verilog code for 8 bit shift register parallel to serial conversion vhdl
    Text: Application Note: CPLD R UARTs in Xilinx CPLDs XAPP341 v1.3 October 1, 2002 Summary This application note provides a functional description of VHDL and Verilog source code for a UART. The code is used to target the XC95144, XCR3128XL, or XC2C128 CPLDs. The


    Original     		PDF XAPP341 XC95144, XCR3128XL, XC2C128 RS232. XAPP341 XCR3128 XCR3128XL vhdl code for rs232 receiver xilinx uart verilog code interface of rs232 to UART in VHDL vhdl code for uart communication vhdl code for serial transmitter vhdl code 16 bit microprocessor uart verilog code verilog code for serial transmitter verilog code for 8 bit shift register parallel to serial conversion vhdl

    SN54LVTH18504A

    Abstract: No abstract text available
    Text: SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS SCBS667B – JULY 1996 – REVISED JUNE 1997 D D D D D D D Members of the Texas Instruments SCOPE  Family of Testability Products


    Original     		PDF SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A 20-BIT SCBS667B LVTH182504A SN74LVTH18504A sctm044 SN54LVTH18504A

    Untitled

    Abstract: No abstract text available
    Text: SN74LVTH18511 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVER WITH BOUNDARY SCAN SCAS694 – MAY 2003 D D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or


    Original     		PDF SN74LVTH18511 18-BIT SCAS694

    Untitled

    Abstract: No abstract text available
    Text: SN74LVTH18511 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVER WITH BOUNDARY SCAN SCAS694 – MAY 2003 D D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or


    Original     		PDF SN74LVTH18511 18-BIT SCAS694 sdyu001x sgyc003d scyb017a sgyn139 scyt126

    XC7236A

    Abstract: MC39I MC-13
    Text:  XC7236A 36-Macrocell CMOS CPLD June 1, 1996 Version 1.0 Product Specification Features This additional ALU in each macrocell can generate any combinatorial function of two sums of products, and it can generate and propagate arithmetic-carry signals between


    Original     		PDF XC7236A 36-Macrocell 44-Pin XC7236A MC39I MC-13

    vhdl code for 8-bit serial adder

    Abstract: vhdl code for 8-bit parity checker vhdl code for 8-bit BCD adder PS74162 vhdl code for 8-bit odd parity checker PS74166 PS74164 vhdl code for 4-bit magnitude comparator vhdl code for asynchronous decade counter vhdl code for 8-bit parity checker using xor gate
    Text: Philips Semiconductors Application note OrCAD Capture Schematic/PHDL Design Flow for Philips CPLDs AMH74 INTRODUCTION Philips Semiconductors provides XPLA Designer and libraries for use with OrCADC Capture at no charge. This allows Capture users to target Philips CPLDs as large as 960 macrocells. This note discusses the use of Philips Hardware


    OCR Scan     		PDF AMH74 vhdl code for 8-bit serial adder vhdl code for 8-bit parity checker vhdl code for 8-bit BCD adder PS74162 vhdl code for 8-bit odd parity checker PS74166 PS74164 vhdl code for 4-bit magnitude comparator vhdl code for asynchronous decade counter vhdl code for 8-bit parity checker using xor gate