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    VCXO 2048 KHZ Search Results

    VCXO 2048 KHZ Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    8N4QV01BG-0001CD Renesas Electronics Corporation Quad-Frequency Programmable VCXO Visit Renesas Electronics Corporation
    81006AKILFT Renesas Electronics Corporation VCXO-to-LVCMOS Outputs Visit Renesas Electronics Corporation
    8N0QV01KH-0098CDI8 Renesas Electronics Corporation Quad-Frequency Programmable VCXO Visit Renesas Electronics Corporation
    3726M-02LFT Renesas Electronics Corporation High Performance VCXO Visit Renesas Electronics Corporation
    MK3727HLF Renesas Electronics Corporation Low Drive 3.3V VCXO Visit Renesas Electronics Corporation

    VCXO 2048 KHZ Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    ETS300

    Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45A MK2069 MT9045 TR62411 crystal 27 MHz
    Text: DATASHEET MK2049-45A 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-45A is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input


    Original     		MK2049-45A MK2049-45A 20-pin TR62411, ETS300 GR-1244 GR-1244 MAN05 MK2049-34 MK2049-36 MK2069 MT9045 TR62411 crystal 27 MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: DATASHEET MK2049-45A 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-45A is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input


    Original     		MK2049-45A MK2049-45A 20-pin TR62411, ETS300 GR-1244 PDF

    ETS300

    Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45 MK2049-45A MT9045 TR62411
    Text: DATASHEET MK2049-45 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-45 is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input


    Original     		MK2049-45 MK2049-45 TR62411, ETS300 GR-1244 50MHz 199707558G GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45A MT9045 TR62411 PDF

    MK2049-45A

    Abstract: MT9045 TR62411 ETS300 GR-1244 MAN05 MK2049-34 MK2049-36 MK2069 FXP MARKING
    Text: DATASHEET MK2049-45A 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-45A is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input


    Original     		MK2049-45A MK2049-45A 20-pin TR62411, ETS300 GR-1244 Stratum284 199707558G MT9045 TR62411 GR-1244 MAN05 MK2049-34 MK2049-36 MK2069 FXP MARKING PDF

    Untitled

    Abstract: No abstract text available
    Text: DATASHEET 3.3 VOLT COMMUNICATIONS CLOCK PLL MK2049-45 Description Features The MK2049-45 is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input


    Original     		MK2049-45 MK2049-45 TR62411, ETS300 GR-1244 50MHz attenuate284 199707558G PDF

    MK2049-45ASILFTR

    Abstract: ETS300 GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45A MT9045 TR62411 vcxo 2048 khz
    Text: DATASHEET MK2049-45A 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-45A is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input


    Original     		MK2049-45A MK2049-45A 20-pin TR62411, ETS300 GR-1244 MK2049-45ASILFTR GR-1244 MAN05 MK2049-34 MK2049-36 MT9045 TR62411 vcxo 2048 khz PDF

    MAN05

    Abstract: MK2049-34 MK2049-36 MK2049-36SI MK2049-45 TR62411 ETS300 GR-1244
    Text: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications


    Original     		MK2049-36 MK2049-36 MAN05 MK2049-34 MK2049-36SI MK2049-45 TR62411 ETS300 GR-1244 PDF

    ETS300

    Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45 TR62411
    Text: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications


    Original     		MK2049-36 MK2049-36 ETS300 GR-1244 MAN05 MK2049-34 MK2049-45 TR62411 PDF

    Untitled

    Abstract: No abstract text available
    Text: DATASHEET 3.3 VOLT COMMUNICATIONS CLOCK PLL M K 2 0 4 9 -3 6 Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications


    Original     		MK2049-36 MK2049-36 PDF

    ETS300

    Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45 TR62411
    Text: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications


    Original     		MK2049-36 MK2049-36 ETS300 GR-1244 MAN05 MK2049-34 MK2049-45 TR62411 PDF

    ETS300

    Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-36SI MK2049-36SITR MK2049-45 TR62411 MK2049-36SILF
    Text: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications


    Original     		MK2049-36 MK2049-36 lead284 199707558G ETS300 GR-1244 MAN05 MK2049-34 MK2049-36SI MK2049-36SITR MK2049-45 TR62411 MK2049-36SILF PDF

    Untitled

    Abstract: No abstract text available
    Text: MK2049-45A 3.3 Volt Communications Clock PLL Description Features The MK2049-45A is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate


    Original     		MK2049-45A MK2049-45A 049-45A PDF

    Untitled

    Abstract: No abstract text available
    Text: MK2049-45 3.3V Communications Clock PLL Description Features The MK2049-45 is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate


    Original     		MK2049-45 MK2049-45 50MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: MK2049-45 3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate


    Original     		MK2049-45 MK2049-45 50MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: MK2049-45 3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate


    Original     		MK2049-45 MK2049-45 50MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: MK2049-45 3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate


    Original     		MK2049-45 MK2049-45 50MHz PDF

    HD-SDI over sdh

    Abstract: stc crystal 6-SOT23 DS1080L DS1081L DS1083L DS1086 DS1086L DS1087L DS1089L
    Text: System Timing & Control 8th Edition February 2009 Spread-spectrum clock modulators reduce peak EMI in LCD panels Pin-selectable dither rate and magnitude reduce radiated emissions by up to 17dB An integrated phase-locked loop PLL modulates the output clock around the center frequency at a pinselectable magnitude, thus reducing peak EMI at fundamental and harmonic frequencies. This is accomplished


    Original     		STC-08 HD-SDI over sdh stc crystal 6-SOT23 DS1080L DS1081L DS1083L DS1086 DS1086L DS1087L DS1089L PDF

    Untitled

    Abstract: No abstract text available
    Text: MK2049-45 3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate


    Original     		MK2049-45 MK2049-45 50MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: DATASHEET COMMUNICATIONS CLOCK JITTER ATTENUATOR MK2058-01 Description Features The MK2058-01 is a VCXO Voltage Controlled Crystal Oscillator based clock jitter attenuator designed for system clock distribution applications. This monolithic IC, combined


    Original     		MK2058-01 MK2058-01 PDF

    TXM TX 2E

    Abstract: 59 PAA MS-026 S-PQFP-G100 TLV320AD13A
    Text: TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE ADSL INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 – AUGUST 2000 D D D D D D Complete Discrete Multitone (DMT)-Based Asymmetric Digital Subscriber Line (ADSL) Coder/Decoder (Codec) Solution


    Original     		TLV320AD13A SLWS109 800-kbit/s 14-Bit 12-Bit TXM TX 2E 59 PAA MS-026 S-PQFP-G100 TLV320AD13A PDF

    TXM TX 2E

    Abstract: VCXO 35.328MHz TNETD
    Text: TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE ADSL INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 – AUGUST 2000 D D D D D D Complete Discrete Multitone (DMT)-Based Asymmetric Digital Subscriber Line (ADSL) Coder/Decoder (Codec) Solution


    Original     		TLV320AD13A SLWS109 800-kbit/s 14-Bit 12-Bit TXM TX 2E VCXO 35.328MHz TNETD PDF

    MAN05

    Abstract: MK2058-01 MK2058-01SI MK2058-01SITR MT9045
    Text: DATASHEET MK2058-01 COMMUNICATIONS CLOCK JITTER ATTENUATOR Description Features The MK2058-01 is a VCXO Voltage Controlled Crystal Oscillator based clock jitter attenuator designed for system clock distribution applications. This monolithic IC, combined


    Original     		MK2058-01 MK2058-01 MAN05 MK2058-01SI MK2058-01SITR MT9045 PDF

    MK2058-01

    Abstract: MAN05 MT9045 mk2058-01silf
    Text: DATASHEET MK2058-01 COMMUNICATIONS CLOCK JITTER ATTENUATOR Description Features The MK2058-01 is a VCXO Voltage Controlled Crystal Oscillator based clock jitter attenuator designed for system clock distribution applications. This monolithic IC, combined


    Original     		MK2058-01 MK2058-01 MAN05 MT9045 mk2058-01silf PDF

    M540K

    Abstract: MAN05 MK2058-01 MK2058-01SI MK2058-01SITR MT9045
    Text: DATASHEET MK2058-01 COMMUNICATIONS CLOCK JITTER ATTENUATOR Description Features The MK2058-01 is a VCXO Voltage Controlled Crystal Oscillator based clock jitter attenuator designed for system clock distribution applications. This monolithic IC, combined


    Original     		MK2058-01 MK2058-01 clocks284 199707558G M540K MAN05 MK2058-01SI MK2058-01SITR MT9045 PDF