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    10126297-L02153SLF Amphenol Communications Solutions 10126297-L02153SLF-PWR LO PRO VTR 2P+15S Visit Amphenol Communications Solutions

    VTR 275 K20 Datasheets Context Search

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    Untitled

    Abstract: No abstract text available
    Text: April 1997 PBL 3796, PBL 3796/2 Subscriber Line Interface Circuit Description Key Features PBL 3796 is an analog Subscriber Line Interface Circuits SLICs , which are fabricated in a 75 V bipolar, monolithic process. The programmable battery feed is resistive with short-loop current limiting. A


    Original     		PDF S-164

    vtr 275 k20

    Abstract: simple and working circuit for ac-dc voltage regulator using SCR 1n4448 diode pbl3799n 3799
    Text: PBL April3799 1997 PBL 3799, PBL 3799/2 Subscriber Line Interface Circuit Description Key Features PBL 3799 is an analog Subscriber Line Interface Circuit SLIC , which is fabricated in a 75 V bipolar, monolithic process. The programmable, resistive feed circuit incorporates a switch mode regulator to


    Original     		PDF April3799 1522-PBL S-164 vtr 275 k20 simple and working circuit for ac-dc voltage regulator using SCR 1n4448 diode pbl3799n 3799

    MB86276

    Abstract: MB8627 MB86833 MD10 V832 YUV422 XC9572XL-TQ100 cid wok
    Text: MB86276 <LIME> Graphics Display Controller Specifications Revision 1.0 18th October, 2006 Copyright FUJITSU LIMITED 2004-2006 ALL RIGHTS RESERVED FUJITSU CONFIDENTIAL <Notes> The specifications in this manual are subject to change without notice. Contact our Sales Department


    Original     		PDF MB86276 MB8627 MB86833 MD10 V832 YUV422 XC9572XL-TQ100 cid wok

    MB86276

    Abstract: A4W14 rgb 8 bit to lvds SCALER
    Text: MB86276 'LIME' Graphics Display Controller Specifications Revision 1.20 19th July, 2011 Copyright FUJITSU LIMITED 2004-2007 ALL RIGHTS RESERVED FUJITSU CONFIDENTIAL Notes The specifications in this manual are subject to change without notice. Contact our Sales Department


    Original     		PDF MB86276 Fujits54 DISP/CAP92 MB86276 A4W14 rgb 8 bit to lvds SCALER

    M28N-1

    Abstract: 0X000
    Text: Freescale Semiconductor Data Sheet Document Number: MSC8158 Rev. 0, 11/2011 MSC8158 Six-Core Digital Signal Processor • Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in


    Original     		PDF MSC8158 MSC8158 SC3850 32-bit M28N-1 0X000

    rc16 e11

    Abstract: MDQ-30 ddr3 pinout MDQ35
    Text: Freescale Semiconductor Data Sheet Document Number: MSC8158E Rev. 0, 11/2011 MSC8158E Six-Core Digital Signal Processor with Security • Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,


    Original     		PDF MSC8158E MSC8158E SC3850 32-bit rc16 e11 MDQ-30 ddr3 pinout MDQ35

    Untitled

    Abstract: No abstract text available
    Text: P1013 QorIQ Integrated Processor Hardware Specifications Datasheet - Preliminary The following list provides an overview of the P1013 feature set: • One High-performance 32-bit e500v2 Core that Implements the Power Architecture Technology: • 36-bit Physical Addressing


    Original     		PDF P1013 P1013 32-bit e500v2 36-bit 400-MHz 1067-MHz

    Untitled

    Abstract: No abstract text available
    Text: P1022 QorIQ Integrated Processor Hardware Specifications Datasheet - Preliminary The following list provides an overview of the P1022 feature set: • Two High-performance 32-bit e500v2 Cores that Implement the Power Architecture Technology: • 36-bit Physical Addressing


    Original     		PDF P1022 P1022 32-bit e500v2 36-bit 400-MHz 1067-MHz 1134Bâ

    Untitled

    Abstract: No abstract text available
    Text: P1013 QorIQ Integrated Processor Hardware Specifications Datasheet - Preliminary The following list provides an overview of the P1013 feature set: • One High-performance 32-bit e500v2 Core that Implements the Power Architecture Technology: • 36-bit Physical Addressing


    Original     		PDF P1013 P1013 32-bit e500v2 36-bit 400-MHz 1067-MHz 1135Bâ

    DDR3 timing diagram

    Abstract: No abstract text available
    Text: P1022 QorIQ Integrated Processor Hardware Specifications Datasheet - Preliminary The following list provides an overview of the P1022 feature set: • Two High-performance 32-bit e500v2 Cores that Implement the Power Architecture Technology: • 36-bit Physical Addressing


    Original     		PDF P1022 P1022 32-bit e500v2 36-bit 400-MHz 1067-MHz DDR3 timing diagram

    10-lane serdes

    Abstract: No abstract text available
    Text: Freescale Semiconductor Data Sheet: Technical Data Document Number: MSC8157 Rev. 1, 12/2012 MSC8157 MSC8157 Six-Core Digital Signal Processor • Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 KB L1 instruction cache, 32 KB L1 data cache, unified 512 KB L2 cache configurable as M2


    Original     		PDF MSC8157 MSC8157 SC3850 32-bit 10-lane serdes

    Untitled

    Abstract: No abstract text available
    Text: Freescale Semiconductor Data Sheet Document Number: MSC8157E Rev. 1, 10/2013 MSC8157E Six-Core Digital Signal Processor with Security • Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,


    Original     		PDF MSC8157E SC3850 32-bit

    Untitled

    Abstract: No abstract text available
    Text: Freescale Semiconductor Data Sheet: Technical Data Document Number: MSC8157 Rev. 2, 10/2013 MSC8157 MSC8157 Six-Core Digital Signal Processor • Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 KB L1 instruction cache, 32 KB L1 data cache, unified 512 KB L2 cache configurable as M2


    Original     		PDF MSC8157 MSC8157 SC3850 32-bit

    10-lane

    Abstract: 10-lane serdes MDQ35 RGMII to SGMII
    Text: Freescale Semiconductor Data Sheet Document Number: MSC8157E Rev. 0, 11/2011 MSC8157E Six-Core Digital Signal Processor with Security • Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,


    Original     		PDF MSC8157E MSC8157E SC3850 32-bit 10-lane 10-lane serdes MDQ35 RGMII to SGMII

    MSC8157SVT1000A

    Abstract: 10-lane 10-lane serdes
    Text: Freescale Semiconductor Data Sheet Document Number: MSC8157 Rev. 0, 11/2011 MSC8157 Six-Core Digital Signal Processor • Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in


    Original     		PDF MSC8157 MSC8157 SC3850 32-bit MSC8157SVT1000A 10-lane 10-lane serdes

    mdq53

    Abstract: ddr3 pinout MSC8157 10-lane serdes 10-lane
    Text: Freescale Semiconductor Data Sheet Document Number: MSC8157_1_2G Rev. 0, 12/2011 MSC8157 1.2 GHz Six-Core Digital Signal Processor • Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,


    Original     		PDF MSC8157 MSC8157 SC3850 32-bit mdq53 ddr3 pinout 10-lane serdes 10-lane

    Untitled

    Abstract: No abstract text available
    Text: Freescale Semiconductor Data Sheet Document Number: MSC8157E Rev. 2, 12/2013 MSC8157E Six-Core Digital Signal Processor with Security • Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,


    Original     		PDF MSC8157E SC3850 32-bit

    Untitled

    Abstract: No abstract text available
    Text: Freescale Semiconductor Data Sheet: Advance Information Document Number: P1010EC Rev. 4, 05/2014 P1010 P1010 QorIQ Integrated Processor Hardware Specifications The following list provides an overview of the P1010 feature set: • High-performance 32-bit Book E-enhanced core based on


    Original     		PDF P1010EC P1010 P1010 32-bit 36-bit 32-Kbyte 1000-MHz 256-Kbyte

    Untitled

    Abstract: No abstract text available
    Text: Freescale Semiconductor Data Sheet: Advance Information Document Number: P1014EC Rev. 4, 05/2014 P1014 P1014 QorIQ Integrated Processor Hardware Specifications The following list provides an overview of the P1014 feature set: • High-performance 32-bit Book E-enhanced core based on


    Original     		PDF P1014EC P1014 P1014 32-bit 36-bit 32-Kbyte 1000-MHz 256-Kbyte

    freescale p1013

    Abstract: No abstract text available
    Text: Freescale Semiconductor Data Sheet: Technical Data Document Number: P1013EC Rev. 2, 9/2013 P1013 P1013 QorIQ Integrated Processor Hardware Specifications The following list provides an overview of the P1013 feature set: • One high-performance 32-bit e500v2 core that implements


    Original     		PDF P1013EC P1013 P1013 32-bit e500v2 36-bit 400-MHz 1067-MHz freescale p1013

    Untitled

    Abstract: No abstract text available
    Text: Freescale Semiconductor Data Sheet: Technical Data Document Number: P1022EC Rev. 2, 9/2013 P1022 P1022 QorIQ Integrated Processor Hardware Specifications The following list provides an overview of the P1022 feature set: • Two high-performance 32-bit e500v2 cores that implement


    Original     		PDF P1022EC P1022 P1022 32-bit e500v2 36-bit 400-MHz 1067-MHz

    QorIQ dhrystone

    Abstract: No abstract text available
    Text: Freescale Semiconductor Data Sheet: Technical Data Document Number: P1023 Rev. 1, 05/2013 P1023 P1023 QorIQ Integrated Processor Data Sheet The following list provides an overview of the chip’s feature set: • High-performance 32-bit Book E-enhanced cores that


    Original     		PDF P1023 P1023 32-bit 36-bit QorIQ dhrystone

    diode 1N4448

    Abstract: driver e8a
    Text: ERICSSO N ^ Aprii 1997 PBL 3799, PBL 3799/2 Subscriber Line Interface Circuit Description Key Features PBL 3799 is an analog Subscriber Line Interface Circuit SLIC , which is fabricated in a 75 V bipolar, monolithic process. The programmable, resistive feed circuit incorporates a switch mode regulator to


    OCR Scan     		PDF 1522-PBL S-164 diode 1N4448 driver e8a

    diode 1N4448

    Abstract: transistor zs 65t ETO thyristor sm 4109 nf2 -12V RELAY Relay RL1, 5V, 100 ohm Nytronics MIS
    Text: ERICSSON g April 1997 PBL 3796, PBL 3796/2 Subscriber Line Interface Circuit Description Key Features PBL 3796 is an analog Subscriber Line Interface Circuits SLICs , which are fabrica­ ted in a 75 V bipolar, monolithic process. The programmable battery feed is resistive with short-loop current limiting. A


    OCR Scan     		PDF 44-pin 32-pin 3796N 3796QN 3796/2QN 3796RN 3796/2RN diode 1N4448 transistor zs 65t ETO thyristor sm 4109 nf2 -12V RELAY Relay RL1, 5V, 100 ohm Nytronics MIS