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spra502

Abstract: TMS320 TMS320C206 TPS7133 TPS7150 TPS7233 TPS7250 3.3v ldo
Contextual Info: Application Report SPRA502 Dual Power Supply Recommendations for the TMS320C206 Steven Voepel Digital Signal Processing Solutions Abstract This document describes two options used to supply power to the Texas Instruments TI TMS320C206 digital signal processor (DSP). The TMS320C206 DSP requires 3.3V for the CPU

Lucent SLC 2000 channel shelf

Abstract: transistor fcs 9013 Lucent SLC 2000 installation sts 9013 DIGRAM FOR TEST IC 324 fcs 9013 fcs 9014 J-D4N SLC 500 ELECTRONIC CIRCUIT DIGRAM transistor fcs 9012
Contextual Info: Preliminary Data Sheet, Rev. 1 October 2000 TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 Features • Versatile IC supports 155/51 Mbits/s SONET/SDH interface solutions for T3/E3, DS2, T1/E1/J1, and DS0/E0/J0 applications. STS/STM Pointer Interpreter

Contextual Info: Preliminary Data Sheet March 2001 TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 Features • ■ Versatile IC supports 155/51 Mbits/s SONET/SDH interface solutions for T3/E3, DS2, T1/E1/J1, and DS0/ E0/J0 applications. Implementation supports both linear 1+1, unprotected and ring (UPSR) network topologies.

LT 7659

Abstract: lin bus example C codes HG123 TMXF281553BAL-2-DB SDH 209 GR-253-CORE JT-G704 JT-G706 TMXF28155 TR-62411
Contextual Info: Preliminary Data Sheet May 2001 TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 1 Features • ■ Versatile IC supports 155/51 Mbits/s SONET/SDH interface solutions for T3/E3, DS2, T1/E1/J1, and DS0/E0/J0 applications. Implementation supports both linear 1 + 1, unprotected and ring (UPSR) network topologies.

LT 7659

Abstract: Lucent SLC 2000 installation LTE DL Channel Encoder transistor fcs 9012 GR-253-CORE JT-G704 JT-G706 TMXF28155 TR-62411 21153 specification update
Contextual Info: Preliminary Data Sheet May 2001 TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 1 Features • ■ Versatile IC supports 155/51 Mbits/s SONET/SDH interface solutions for T3/E3, DS2, T1/E1/J1, and DS0/E0/J0 applications. Implementation supports both linear 1 + 1, unprotected and ring (UPSR) network topologies.

Contextual Info: LS125 Data Sheet I-Cube SATC Controller Description Features 33 M Hz 32-bit PCI bus interface, 8 interrapt lines to support up to 8 LS port controllers. 32 or 48 bit Interface with standard asynchronous SRAM to internal port map registers cache up to 128K MAC addresses.