telcordia gr 1081 core
Abstract: No abstract text available
Text: xr XRT75R03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER MARCH 2005 REV. 1.0.3 GENERAL DESCRIPTION TRANSMITTER: The XRT75R03D is a three-channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless Redundancy)
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XRT75R03D
XRT75R03D
telcordia gr 1081 core
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CHN G4 309
Abstract: 40 serice free DMO 565 R CHN 932
Text: xr XRT86L38 PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO JANUARY 2005 REV. P1.1.7 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .
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XRT86L38
XRT86L38
CHN G4 309
40 serice free
DMO 565 R
CHN 932
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chn 542
Abstract: No abstract text available
Text: xr XRT86VL32 PRELIMINARY DUAL T1/E1/J1 FRAMER/LIU COMBO FEBRUARY 2005 REV. P1.0.3 GENERAL DESCRIPTION The XRT86VL32 is a two-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .
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XRT86VL32
XRT86VL32
chn 542
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DMO 565 R
Abstract: chn 924 CHN G4 120
Text: xr XRT86L30 PRELIMINARY SINGLE T1/E1/J1 FRAMER/LIU COMBO JUNE 2005 REV. P1.0.2 GENERAL DESCRIPTION The XRT86L30 is a single channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .
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XRT86L30
XRT86L30
DMO 565 R
chn 924
CHN G4 120
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DMO 565 R
Abstract: chn 631 CHN 534 CHN 633 diode ST chn 624 TR54016 XRT84V24 XRT86L34 XRT86L34IB E1 frame
Text: xr XRT86L34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO DECEMBER 2004 REV. P1.1.7 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .
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XRT86L34
XRT86L34
DMO 565 R
chn 631
CHN 534
CHN 633 diode
ST chn 624
TR54016
XRT84V24
XRT86L34IB
E1 frame
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chn 751
Abstract: GR-253 GR-253-CORE GR-499-CORE XRT75R06D XRT75R06DIB chn 622 st WG 253 chn 834 HDB3 CODING DECODING FPGA
Text: xr XRT75R06D PRELIMINARY SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER JULY 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRT75R06D is a six channel fully integrated Line Interface Unit LIU featuring EXAR’s R3 Technology (Reconfigurable, Relayless, Redundancy) for E3/
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XRT75R06D
XRT75R06D
chn 751
GR-253
GR-253-CORE
GR-499-CORE
XRT75R06DIB
chn 622 st
WG 253
chn 834
HDB3 CODING DECODING FPGA
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dmo 265
Abstract: CHN 923 P118 TR54016
Text: xr XRT86L34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO JANUARY 2005 REV. P1.1.8 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .
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XRT86L34
XRT86L34
dmo 265
CHN 923
P118
TR54016
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SDH 209
Abstract: DMO 565 R SCR PIN CONFIGURATION CHN 035 CHN G4 309 telephone schemes sa8316 dmo 265 CHN G4 329
Text: xr XRT86VL38 PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO MARCH 2005 REV. P1.0.6 GENERAL DESCRIPTION The XRT86VL38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .
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XRT86VL38
XRT86VL38
SDH 209
DMO 565 R
SCR PIN CONFIGURATION CHN 035
CHN G4 309
telephone schemes
sa8316
dmo 265
CHN G4 329
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DMO 565 R
Abstract: dmo 465 Twelve NC Code
Text: xr XRT86L34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO NOVEMBER 2004 REV. P1.1.6 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .
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XRT86L34
XRT86L34
DMO 565 R
dmo 465
Twelve NC Code
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DMO 565 R
Abstract: No abstract text available
Text: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - ATM ARCHITECTURAL DESCRIPTION NOVEMBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter
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XRT79L71
XRT79L71
DMO 565 R
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DMO 565 R
Abstract: SCR PIN CONFIGURATION CHN 035 tp 147
Text: xr XRT86VL34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO JUNE 2005 REV. P1.0.4 GENERAL DESCRIPTION The XRT86VL34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .
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XRT86VL34
XRT86VL34
DMO 565 R
SCR PIN CONFIGURATION CHN 035
tp 147
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RxFr1544
Abstract: No abstract text available
Text: xr XRT86VL32 PRELIMINARY DUAL T1/E1/J1 FRAMER/LIU COMBO JUNE 2005 REV. P1.0.4 GENERAL DESCRIPTION The XRT86VL32 is a two-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .
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XRT86VL32
XRT86VL32
RxFr1544
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CHN 523
Abstract: HDB3 CODING DECODING FPGA chn 752 chn 751 chn 720 GR-253 GR-253-CORE GR-499-CORE XRT75L06D XRT75L06DIB
Text: xr XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER APRIL 2005 REV. 1.0.4 GENERAL DESCRIPTION attenuators can be used for clock smoothing in SONET STS-1 to DS-3 de-mapping. The XRT75L06D is a six channel fully integrated Line
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XRT75L06D
XRT75L06D
CHN 523
HDB3 CODING DECODING FPGA
chn 752
chn 751
chn 720
GR-253
GR-253-CORE
GR-499-CORE
XRT75L06DIB
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dmo 465
Abstract: No abstract text available
Text: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - PPP ARCHITECTURAL DESCRIPTION DECEMBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter
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XRT79L71
XRT79L71
dmo 465
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dmo 565 r
Abstract: CHN 522 chn 542 chn 621 CHN 616 CHN 507 chn 638 chn 537 chn 543 CHN 618
Text: xr XRT86VL32 PRELIMINARY PRELIMINARY DUAL T1/E1/J1 FRAMER/LIU COMBO SEPTEMBER 2004 REV. P1.0.1 GENERAL DESCRIPTION The XRT86VL32 is a two-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VL32 provides protection
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XRT86VL32
XRT86VL32
dmo 565 r
CHN 522
chn 542
chn 621
CHN 616
CHN 507
chn 638
chn 537
chn 543
CHN 618
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F46C
Abstract: F487 F65D F61C b1167 F47B F45E F48B F487 transistor 36B2
Text: National Semiconductor Application Note 487 Ashok Krishnamurthy April 1987 INTRODUCTION This report describes the implementation of a radix-2 Decimation-in-time FFT algorithm on the HPC The program as presently set up can do FFTs of length 2 4 8 16 32 64 128 and 256 The program can be easily modified to work
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PM8921
Abstract: pm8926 PM8922 LP 8029 Leader 8020 schematics Oscilloscope PM8931 philips pm8922 LP-16BX p6103 mp 9141 es
Text: Table of Contents Lead & Cable Length Information, Ordering Information, Field Servicing Information.01 Conversion
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X2015.
203XM-3-262
PM8921
pm8926
PM8922
LP 8029
Leader 8020 schematics Oscilloscope
PM8931
philips pm8922
LP-16BX
p6103
mp 9141 es
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IC 741 OPAMP
Abstract: SAA 1251 7106CPL TDA2620 SAA1121 LM 4440 AUDIO AMPLIFIER CIRCUIT touch dimmer TC 306H TDA 2310 TDA 2060 7107CPL
Text: Lineaire IC’s Lineaire IC’s dil to 99 dil 8 to 99 dil 18 to 78 to 99 dil 20 to 99 cer dip to 78 Wij leveren een groot aantal lineaire ic's uit voorraad. Kunt u een bepaald type niet vinden, aarzel dan niet ons telefonisch te raadplegen. Veelal kunnen wij u op korte
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XR558
Abstract: XR558CP 558CP XR-558CP xr 558 XR-558 XR-559 XR559CP XR-559CP 559CP
Text: Z *E X flR XR-558/559 Quad Timing Circuits FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The XR-558 and the XR-559 quad tim ing circuits con tain four independent tim er sections on a single m ono lithic chip. Each of the tim er sections on the chip are
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XR-558
XR-559
ouS232C
XR-1488
RS232C
XR-1489A
XR558
XR558CP
558CP
XR-558CP
xr 558
XR559CP
XR-559CP
559CP
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XR-082
Abstract: XR-082CP TL083 XR082CP XR-083 XR-082CN Xr083 XR-082 N XR082M OP tl 082
Text: Z * EX4R XR-082/083 Dual Bipolar JFET Operational Amplifier FUNCTIONAL BLOCK DIAGRAMS GENERAL DESCRIPTION The XR-082/XR-083 family of dual bipolar JF E T opera tional amplifiers are designed to offer higher perform ance than conventional bipolar op amps. Each amplifier
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XR-082/083
XR-082/XR-083
XR-082
XR-083
XR-1488
S232C
XR-1489A
XR-1488N
XR-1488P
XR-1489AN
XR-082CP
TL083
XR082CP
XR-082CN
Xr083
XR-082 N
XR082M
OP tl 082
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50hz notch filter ic
Abstract: XR102 xr4194 1640Hz LM79L05AC XR-5532 1khz bandpass XR-1020 R-1020A xr-1020a
Text: JSTEXAR_ XR-1020A Telecom Instrumentation Filter PIN ASSIGNMENT GENERAL DESCRIPTION The XR-1020A is a data communication/telecommuni cation instrumentation filter. This device provides ten of the filters used to characterize communication links for
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XR-1020A
XR-1020A
1010Hz)
825Hz)
15kHz
50hz notch filter ic
XR102
xr4194
1640Hz
LM79L05AC
XR-5532
1khz bandpass
XR-1020
R-1020A
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88C681
Abstract: 68C681 explain the 8288 bus controller 88c681j 80286 schematic 8085 schematic with hardware reset
Text: XR-88C681 CMOS Dual Channel UART DUART August 1997-2 FEATURES Two Full Duplex, Independent Channels Asynchronous Receiver and Transmitter Quadruple-Buffered Receivers and Dual Buffered Transmitters Programmable Stop Bits in 1/16 Bit Increments Internal Bit Rate Generators with More than 23 Bit
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XR-88C681
XR-88C681
-15pF+
6864MHz
6864MHz
88C681
68C681
explain the 8288 bus controller
88c681j
80286 schematic
8085 schematic with hardware reset
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6d40 Wiring diagram
Abstract: DP8302 IC TTL 7400 diagram and truth table DM9318 M5246 69C0 MM5214 DP8300 MM2101 stk 412 210
Text: PACE Microprocessor System Design Manual National Semiconductor Publication Number 420305292-001A Order Number IPC-16A/928 March 1977 $5.00 PACE Processing And Control Element Microprocessor System Design Manual National Semiconductor Corporation 2900 Semiconductor Drive
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20305292-001A
IPC-16A/928
J28592
ipc-16a/928
da-dd10m37
6d40 Wiring diagram
DP8302
IC TTL 7400 diagram and truth table
DM9318
M5246
69C0
MM5214
DP8300
MM2101
stk 412 210
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stk 412 -410
Abstract: stk 5315 STK 419 150 IRF CANAL P stk 412 -420 STK 412 150 equivalent stk 412 750 LTM 4620 component data D965 equivalent
Text: Microprocessor Assembly Language Programming Manual National Semiconductor Publication Number 4200130A Order Number IPC-16S/969Y January 1977 PACE Processing And Control Element Assembly Language Programming Manual National Semiconductor Corporation 2900 Semiconductor Drive
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200130A
IPC-16S/969Y
200130A,
IPC-16S
DD10M17
stk 412 -410
stk 5315
STK 419 150
IRF CANAL P
stk 412 -420
STK 412 150 equivalent
stk 412 750
LTM 4620
component data
D965 equivalent
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