DSAUD0072978.pdf by Maxim Integrated Products

Partial File Text 19-5870; Rev 0; 5/11 Memory-Mapped SHA-1 Coprocessor The DSSHA1 coprocessor with 64-byte RAM is a synthesizable register transfer level (RTL) implementation of the FIPS 180-3 Secure Hash Algorith
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C-l018 CL018G DS1961S DS1963S DS2460 DS28CN01 DS28E01-100 DS28E02 DS28E10

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