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DSA00249587.pdf
Manufacturer
Cypress Semiconductor
Partial File Text
CY2SSTU877 PRELIMINARY 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features distributes a differential clock input pair (CK, CK#) to ten differential pair of clock outputs (Y
Datasheet Type
Original
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User Tagged Keywords
CY2SSTU877
CY2SSTU877BVXC-32
CY2SSTU877BVXC-32T
CY2SSTU877BVXI-32
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