DSA00123464.pdf by Fairchild Semiconductor

Partial File Text DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs sition time of the negative going edge of the clock pulse. Data on the J and K inpu
Datasheet Type Original
RoHS No
Pb Free Unknown
Lifecycle Obsolete
Price & Stock
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Equivalent Parts !
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DM74S112 N74S112N 74S112PC N74S112N N74S112B

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