DSA0077280.pdf by Hitachi Semiconductor

Partial File Text 1.2 Internal Block Diagram PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Port A ROM (Flash memory) Peripheral address bus Port F PC break controller (2 channels
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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