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DSA00102482.pdf
by Xilinx
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P1 TTL0 P1 D3 A1 TTL3 A2 TTL6 A3 TTL9 A4 AID6 D2 D1 S1-31 S1-33 S1-36 S1-37 TTL1 P1 D4 B1 TTL4 S1-30 S1-27 D6 B2 TTL2 TTL5 D5 C1
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