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    Part Img 74HC107D,652 datasheet by NXP Semiconductors

    • Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with... Reset; Negative-Edge Trigger ; F<sub>max</sub>: 78 MHz; Logic switching levels: CMOS ; Number of pins: 14 ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 16@5V ns; Voltage: 2.0-6.0 V; Package: SOT108-1 (SO14); Container: Bulk Pack, CECC more
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    74HC107D,652 datasheet preview

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