74HCT107D,652 datasheet by NXP Semiconductors

Description Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger; TTL Enabled ; F<sub>max</sub>: 73 MHz; Logic switching levels: TTL ; Number of pins: 14 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 16 ns; Voltage: 4.5-5.5V; Package: SOT108-1 (SO14); Container: Bulk Pack, CECC
Datasheet Type Original
RoHS Yes
Pb Free Unknown
Lifecycle Transferred
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74HCT107D,652 datasheet preview Download Datasheet