74HCT112D-T datasheet by NXP Semiconductors

Description dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; F<sub>max</sub>: 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V
Datasheet Type Original
RoHS Yes
Pb Free Unknown
Lifecycle Obsolete
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933714970653 74HCT112D,652 GD54HCT112D 74HCT112D

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