DSAFRAZ0017889.pdf by Renesas Technology

Partial File Text 1.2 Internal Block Diagram Port A WDT1 (subclock) 8-bit timer (4 channels) ROM Port F PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 Por
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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