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DSAIHSC00038545.pdf
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QL3040 / QL3040R 40,000 Usable PLD Gate pASIC®3 FPGA Combining High Performance and High Density PRELIMINARY DATA pASIC 3 HIGHLIGHTS ... 40,000 usable PLD gates, 252 I/O pins 20,736 bit
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Scan
ECAD Model
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