DSAEDA00051120.pdf by Analog Devices

Partial File Text FUNCTIONAL BLOCK DIAGRAM SER/PAR D0 D1 D2 D3 D4 A0 A1 A2 A3 CLK 80-BIT SHIFT REGISTER WITH 5-BIT PARALLEL LOADING DATA IN UPDATE 80 PARALLEL LATCH CE RESET 80 DECODE 16 Ø
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