DSA00164971.pdf by Cypress Semiconductor

Partial File Text PRELIMINARY CY7C1326H 2-Mbit (128K x 18) Pipelined Sync SRAM Features · Registered inputs and outputs for pipelined operation · 128K × 18 common I/O architecture · 3.3V core power supply · 3.3
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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