DSA00161937.pdf by Cypress Semiconductor

Partial File Text PRELIMINARY Delta39KTM ISRTM CPLD Family CPLDs at FPGA DensitiesTM 1 Features ·High density -- 15K to 350K usable gates -- 256 to 5376 macrocells -- 92 to 520 maximum I/O pins -- 12 Dedicat
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1kx8 rom 250NTC NT208