DSA00161664.pdf by Cypress Semiconductor

Partial File Text PRELIMINARY Delta39KTM ISRTM CPLD Family CPLDs at FPGA DensitiesTM Features ·High density -- 15K to 350K usable gates -- 256 to 5376 macrocells -- 92 to 520 maximum I/O pins -- 12 Dedicated In
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"Single-Port RAM" CY39100V484-125BBI

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