CY7C2568KV18-500BZC datasheet
by Cypress Semiconductor
- 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT; Architecture: DDR-II+ CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
- Original
- No
- Unknown
- Obsolete
- Find it at Findchips.com
