DSASW00213921.pdf by Integrated Silicon Solution

Partial File Text 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs A October 2010 Features · 2M x 36 or 4M x 18. · On-chip delay-locked loop (DLL) for wide data valid window. · Separate read an
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D0-35 IS61QDB22M36 IS61QDB24M18