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DSA001508.pdf
Manufacturer
Altera
Partial File Text
Implementing a 100,000-Gate Gate Array Design in an EPF10K100 Device TECHNI CA L B RI E F 1 5 MA R C H 1 997 The EPF10K100 device--a member of the Altera® FLEX® 10K family--is the lar
Datasheet Type
Original
ECAD Model
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User Tagged Keywords
digital clock using gates
digital clock using logic gates
EPF10K100
fft algorithm
LCA500K
memory compiler
twiddle