DSA00291847.pdf by Cypress Semiconductor

Partial File Text CY7C1328G 4-Mbit (256K x 18) Pipelined DCD Sync SRAM Functional Description[1] Features · Registered inputs and outputs for pipelined operation · Optimal for performance (Double-Cycle deselec
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CY7C1328G CY7C1328G-133AXC CY7C1328G-133AXI CY7C1328G-166AXC CY7C1328G-200AXC