DSAH00133428.pdf by Cypress Semiconductor

Partial File Text CY7C1268XV18, CY7C1270XV18 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Feat
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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3M Touch Systems