This site uses third-party website tracking technologies to provide and continually improve our services, and to display advertisements according to users' interests. I agree and may revoke or change my consent at any time with effect for the future.
ADVANCE
l ^ lld R O N
M T48LC 4M 4R 1(S ) 4 MEG X 4 SDRAM
SYNCHRONOUS DRAM
FEATURES
ยท Fully synchronous; all signals (excluding clock enable) registered to positive edge of system clock Mee
