The Datasheet Archive
Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers
Search
DSASW00106101.pdf
Manufacturer
Altera
Partial File Text
Architecture and Methodology of a SoPC with 3.25Gbps CDR based Serdes and 1Gbps Dynamic Phase Alignment Ramanand Venkata, Wilson Wong, Tina Tran, Vinson Chan, Tim Hoang, Henry Lui, Binh Ton, Sergey
Datasheet Type
Original
ECAD Model
Part Details
Part pricing, stock, data attributes from Findchips.com
DSASW00106101.pdf preview
Download Datasheet
User Tagged Keywords
"toan nguyen"
1gbps serdes
200MHZ
altera 48 fpga
altera ethernet packet generator
CF031-1
circuit diagram digital clocks
fpga da altera
FPGA SoC, Chip, telecom
infiniband Physical Medium Attachment
Serial RapidIO Infiniband
xaui xgmii ip core altera
Price & Stock Powered by
Findchips