DSA00388279.pdf by Xilinx

Partial File Text Application Note: Spartan-3 Generation FPGA Families Inverting LVDS Signals for Efficient PCB Layout in Spartan-3 Generation FPGAs R Author: Nick Sawyer and Gary Lawman XAPP491 (v1.0) Oct
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lvds vhdl LVDS-25 LVDS25 oddr2 oddr2 verilog Spartan 3E VHDL code verilog code for combinational loop verilog code for lvds driver verilog code for transmission line vhdl code for bus invert coding circuit vhdl code for DCM vhdl code for lvds driver vhdl code for multiplexer 8 to 1 with inverter XAPP491