DSAEDA000132912.pdf by Cypress Semiconductor

Partial File Text CY7C1146KV18, CY7C1157KV18 CY7C1148KV18, CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Configurations Features I 18 Mbit density (2 M x 8, 2 M x 9
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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