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DSA0066701.pdf
Manufacturer
Analog Devices
Partial File Text
Preliminary Technical Data FEATURES Low phase noise, phase-locked loop (PLL) Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVDS, or
Datasheet Type
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ECAD Model
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JESD51-6