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    Scans-0031473.pdf

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    • QL2009 9,000 Gate 3.3V and 5.0V pASIC® 2 FPGA Combining Speed, Density, Low Cost and Flexibility PRELIMINARY DATA Rev. B pASIC 2 HIGHLIGHTS ... 9,000 usable gates, 225 I/O pins QL2009 Block
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    cadence xa 125 2 PQ208 QL2009 QL2009-1PB256C QL2009-1PF144C QL2009-1PQ208C
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