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DSASW0010764.pdf
Manufacturer
PMC-Sierra
Partial File Text
RM7000C Released 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache FEATURES 16 Kbytes instruction, 16 Kbytes data, 256 Kbytes on-chip secondary. ยท Per line cache locking in primaries
Datasheet Type
Original
ECAD Model
Part Details
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User Tagged Keywords
16 bit single cycle mips
GT-6424
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l2 cache controller mips
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RM5271
RM7000
RM7000A
RM7000B
RM7000C