pdc 140
Abstract: DL140 E195 MC100E195 MC10E195
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.
|
Original
|
MC10E195
MC100E195
MC10E/100E195
DL140
MC10E195/D*
MC10E195/D
pdc 140
E195
MC100E195
MC10E195
|
PDF
|
DL140
Abstract: E195 MC100E195 MC10E195
Text: MOTOROLA Order this document by MC10E195/D SEMICONDUCTOR TECHNICAL DATA MC10E195 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.
|
Original
|
MC10E195/D
MC10E195
MC100E195
MC10E/100E195
DL140
E195
MC100E195
MC10E195
|
PDF
|
E195
Abstract: SY100E195 SY10E195 SY10E195JC
Text: Micrel, Inc. PROGRAMMABLE DELAY CHIP FEATURES SY10E195 100E195 DESCRIPTION • Up to 2ns delay range ■ Extended 100E VEE range of –4.2V to –5.5V ■ ■ ■ ■ ■ ■ Precison Edge SY10E195 Precison 100E195 Edge® The SY10/100E195 are programmable delay chips
|
Original
|
SY10E195
SY100E195
SY10/100E195
M9999-032006
E195
SY100E195
SY10E195
SY10E195JC
|
PDF
|
TRANSISTOR D 1765 720
Abstract: 100E195 E195 MC100E195 MC10E195
Text: MC10E195, 100E195 5V ECL Programmable Delay Chip Description The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in
|
Original
|
MC10E195,
MC100E195
MC10E/100E195
MC10E195/D
TRANSISTOR D 1765 720
100E195
E195
MC100E195
MC10E195
|
PDF
|
E195
Abstract: MC100E195 MC100E195FN MC100E195FNR2 MC10E195 MC10E195FN MC10E195FNR2
Text: MC10E195, 100E195 5VĄECL Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in
|
Original
|
MC10E195,
MC100E195
MC10E/100E195
r14525
MC10E195/D
E195
MC100E195
MC100E195FN
MC100E195FNR2
MC10E195
MC10E195FN
MC10E195FNR2
|
PDF
|
3870
Abstract: No abstract text available
Text: MC10E195, 100E195 5V ECL Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in
|
Original
|
MC10E195,
MC100E195
MC10E/100E195
BRD8011/D.
MC100E195
AN1405/D
AN1406/D
AN1503/D
AN1504/D
3870
|
PDF
|
Untitled
Abstract: No abstract text available
Text: MC10E195, 100E195 5V ECL Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in
|
Original
|
MC10E195,
MC100E195
MC10E/100E195
MC10E195/D
|
PDF
|
MC10E195FN
Abstract: E195 MC100E195 MC100E195FN MC100E195FNR2 MC10E195 MC10E195FNR2 100E195
Text: MC10E195, 100E195 5VĄECL Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in
|
Original
|
MC10E195,
MC100E195
MC10E/100E195
r14525
MC10E195/D
MC10E195FN
E195
MC100E195
MC100E195FN
MC100E195FNR2
MC10E195
MC10E195FNR2
100E195
|
PDF
|
ic 1240 equivalent ics
Abstract: digital clock using logic gates 1-BIT D Latch D7 120 en 4020 TRANSISTOR D 1765 720 BUS BAR specification marking code onsemi Diode A6 MC100E195 pecl logic voltage levels
Text: MC10E195, 100E195 5V ECL Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in
|
Original
|
MC10E195,
MC100E195
MC10E/100E195
MC10E195/D
ic 1240 equivalent ics
digital clock using logic gates
1-BIT D Latch
D7 120
en 4020
TRANSISTOR D 1765 720
BUS BAR specification
marking code onsemi Diode A6
MC100E195
pecl logic voltage levels
|
PDF
|
100E195
Abstract: E195 MC100E195 MC10E195
Text: MC10E195, 100E195 5V ECL Programmable Delay Chip Description The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in
|
Original
|
MC10E195,
MC100E195
MC10E/100E195
MC10E195/D
100E195
E195
MC100E195
MC10E195
|
PDF
|
TRANSISTOR D 1765 720
Abstract: E195 MC100E195 MC100E195FN MC100E195FNR2 MC10E195 MC10E195FN MC10E195FNR2
Text: MC10E195, 100E195 5VĄECL Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in
|
Original
|
MC10E195,
MC100E195
MC10E/100E195
r14525
MC10E195/D
TRANSISTOR D 1765 720
E195
MC100E195
MC100E195FN
MC100E195FNR2
MC10E195
MC10E195FN
MC10E195FNR2
|
PDF
|
Untitled
Abstract: No abstract text available
Text: MC10E195, 100E195 5V ECL Programmable Delay Chip Description The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in
|
Original
|
MC10E195,
MC100E195
MC10E/100E195
MC10E195/D
|
PDF
|
Untitled
Abstract: No abstract text available
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 M 100E195 Program m able Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay ot a differential ECL input transition.
|
OCR Scan
|
MC10E195
C100E195
MC10E/100E195
DL140
|
PDF
|
Untitled
Abstract: No abstract text available
Text: MOTOROLA Order this document by MC10E195/D SEMICONDUCTOR TECHNICAL DATA M C 10E195 M C 100E195 Program m able D elay Chip The MC1OE/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable
|
OCR Scan
|
MC10E195/D
MC1OE/100E195
|
PDF
|
|
Untitled
Abstract: No abstract text available
Text: * PROGRAMMABLE DELAY CHI P SYNERGY SEMICONDUCTOR I FEATURES_ • ■ Up to 2ns delay range ■ 20ps/digital step resolution ■ >1 GHz bandwidth ■ On-chip cascade circuitry ■ ESD protection of 2000V ■ Fully compatible with Motorola MC10E/100E195
|
OCR Scan
|
SY10E195
SY100E195
20ps/digital
MC10E/100E195
J28-1
J28-1
|
PDF
|
Untitled
Abstract: No abstract text available
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C10E195 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL Input transition.
|
OCR Scan
|
C10E195
MC100E195
MC10E/100E195
DL140
|
PDF
|
Untitled
Abstract: No abstract text available
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.
|
OCR Scan
|
MC10E195
MC100E195
MC10E/100E195
3b7252
DL140
|
PDF
|
E195
Abstract: SY100E195 SY100E195JC SY10E195 SY10E195JC SY10E195JCTR
Text: * SYNERGY P R O G RAM M A BLE DELAY CHIP S E M IC O N D U C T O R F E A TU R E S Up to 2ns delay range ESD protection of 2000V Fully compatible with Motorola MC10E/100E195 PIN C O N FIG U R A T IO N oj Û Di ^ 26 Do 27 co *<r m Cl Q Q q fs. j z q n n n n n n n
|
OCR Scan
|
SY10E195
SY100E195
20ps/digital
MC10E/100E195
SY10/100E195
SY10E195
SY10E195JC
J28-1
SY10E195JCTR
E195
SY100E195
SY100E195JC
|
PDF
|
Untitled
Abstract: No abstract text available
Text: * PROGRAMMABLE DELAY CHIP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Up to 2ns delay range ~20ps/digital step resolution >1GHz bandwidth On-chip cascade circuitry ESD protection of 2000V Fully compatible with Motorola MC10E/100E195 PIN CONFIGURATION N CO T
|
OCR Scan
|
20ps/digital
MC10E/100E195
SY10E195
SY100E195
SY10E195JC
J28-1
SY10E195JCTR
|
PDF
|
Untitled
Abstract: No abstract text available
Text: w Y 3? W >R DESCRIPTION • Up to 2ns delay range ■ Extended 100E V ee range of -4 .2 V to -5 .5 V ■ =20ps/digitai step resolution ■ >1 GHz bandwidth ■ On-chip cascade circuitry ■ 75Kki2 input pulldown resistor ■ Fully com patible with M otorola MC10E/100E195
|
OCR Scan
|
Y10E195
20ps/digitai
75Kki2
MC10E/100E195
28-pin
32-gate
SY10E195
SY100E195
SY10E195JC
SY10E195JCTR
|
PDF
|
Untitled
Abstract: No abstract text available
Text: bfiE D MOTOROLA • SEMICONDUCTOR bBb7ES5 OOTM'ÌVM EÔG m o m MOTOROLA SC LOÙIC I TECHNICAL DATA MC10E195 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip (PDC) designed primarily for clock de-skewlng and timing adjustment. It provides variable
|
OCR Scan
|
MC10E195
MC100E195
MC10E/100E195
|
PDF
|
Untitled
Abstract: No abstract text available
Text: MOTOROLA O rder this docum ent by M C10E195/D SEMICONDUCTOR TECHNICAL DATA MC10E195 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.
|
OCR Scan
|
C10E195/D
MC10E195
MC100E195
MC10E/100E195
|
PDF
|
Untitled
Abstract: No abstract text available
Text: *SYNERGY PR O G R A M M A B LE DELAY CHIP SEMICONDUCTOR FEATURES Clockworks SY10E195 100E195 DESCRIPTION Up to 2ns delay range =£Ops/digital step resolution >1GHz bandwidth On-chip cascade circuitry ESD protection of 2000V Fully compatible with Motorola MC10E/100E195
|
OCR Scan
|
SY10E195
SY100E195
MC10E/100E195
10/100E
SY10E195JC
SY10E195JCTR
SY100E195JC
SY100E195JCTR
|
PDF
|
Untitled
Abstract: No abstract text available
Text: * PROGRAMMABLE DELAY CHIP SYNERGY SEM IC O N D U C TO R FEATURES • ■ C lo c k w o r k s ' SY10E195 S Y 10Q E 195 DESCRIPTION Up to 2ns d e la y range 2 0 p s /d ig ita l s te p re s o lu tio n ■ >1 GHz b a n d w id th ■ O n -c h ip c a sca d e c irc u itry
|
OCR Scan
|
SY10E195
10E/100E195
SY10/100E195
SY100E195
SY10E195JC
SY100E195JC
J28-1
J28-1
|
PDF
|