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128X36 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
verilog hdl code for matrix multiplication Abstract: vhdl code for pipelined matrix multiplication vhdl code hamming verilog code for matrix multiplication vhdl code for matrix multiplication vhdl code hamming edac memory Core from Libero verilog code hamming hamming code FPGA vhdl coding for hamming code Text: Application Note AC319 Using EDAC RAM for RadTolerant RTAX-S/SL and Axcelerator FPGAs Applies to EDAC Core from Libero IDE v7.2 and Newer Introduction The newest Actel designed-for-space field programmable gate array FPGA family, RTAX-S/SL, is a highperformance, high-density, antifuse-based FPGA with embedded user static RAM (SRAM). Based on the	Original	PDF	AC319 verilog hdl code for matrix multiplication vhdl code for pipelined matrix multiplication vhdl code hamming verilog code for matrix multiplication vhdl code for matrix multiplication vhdl code hamming edac memory Core from Libero verilog code hamming hamming code FPGA vhdl coding for hamming code
OLED Abstract: No abstract text available Text: 1/1 有機ELディスプレイモノカラー・パッシブマトリクス方式 RoHS指令対応製品 UEL シリーズ UEL316 形状・寸法 21.7 25.9 0.9 0.4 9.0 6.1 ∗∗∗∗∗∗∗∗ 21.7 12.3 0.3 1.8 26.6 2.4 Printing position of Lot.No.	Original	PDF	UEL316 36dots) 25pin 140max. 2002/95/EC uel316 OLED
1kx4 Abstract: ALTERA MAX 3000 Altera MAX V CPLD PQFP ALTERA 160 Q302 EP1C12 altera TQFP 32 PACKAGE altera cyclone 3 F324 Altera Text: Семейство Cyclone Copyright 2003 Altera Corporation 1 Семейства микросхем Altera Семейства программируемой логики – FPGA высокой и средней степени интеграции;	Original	PDF	EPC16) 1kx4 ALTERA MAX 3000 Altera MAX V CPLD PQFP ALTERA 160 Q302 EP1C12 altera TQFP 32 PACKAGE altera cyclone 3 F324 Altera
pin configuration of 7496 IC Abstract: TMS 3617 Transistor TT 2246 ttl to mini-lvds EP2C35F672 IC 4033 pin configuration EP2C20F256 CI 4017 combinational digital lock circuit projects EP2C8F256 Text: Cyclone II Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CII5V1-3.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and	Original	PDF
asynchronous fifo vhdl Abstract: 8 BIT ALU design with verilog/vhdl code full subtractor using ic 74138 74139 for bcd to excess 3 code vhdl code for 8bit bcd to seven segment display 32 BIT ALU design with verilog/vhdl code 74594 16 BIT ALU design with verilog/vhdl code B1516 RAM1024 Text: QuickWorks User Manual with SpDE Reference Release 2009.2.1 Contact Information QuickLogic Corporation 1277 Orleans Drive Sunnyvale, CA 94089 Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932-57-9011 (Europe) +(852) 2567-5441 (Asia) E-mail: info@quicklogic.com	Original	PDF
LGA 478 SOCKET PIN LAYOUT Abstract: RTAX2000 Text: v5.2 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg	Original	PDF	TM1019 LGA 478 SOCKET PIN LAYOUT RTAX2000
Untitled Abstract: No abstract text available Text: Advanced v0.3  RTAX-S Family FPGAs Sp e ci a l F ea t ur es f o r Sp a ce • Up to 10,752 SEU Hardened Flip-Flops Eliminate Software TMR Necessity >LET th 37 LET, GEO SEU Rate <10-10 Errors/Bit-Day • Expected SRAM Upset Rate of <10-10 Errors/Bit-Day with	Original	PDF	32-Bits 114specifications
RTAX2000 Abstract: schematic diagram 2 sc 1020 RTAX1000 RTAX250 Synplify tmr RTAX2000S Text: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case	Original	PDF	TM1019 com/documents/CQ352FPGA RTAX2000 schematic diagram 2 sc 1020 RTAX1000 RTAX250 Synplify tmr RTAX2000S
RTAX2000 Abstract: TB125 24mA-drive 352-Pin Text: RTAX-S RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment Clamp Diode Hot Insertion 5V Tolerance Input Buffer Output Buffer LVTTL No Yes No Enabled/Disabled 3.3V PCI Yes No Yes1 Enabled/Disabled LVCMOS2.5V No Yes	Original	PDF	JESD8-11) RTAX2000 TB125 24mA-drive 352-Pin
RTAX2000 Abstract: footprint cqfp 280 RTAX1000S actel cqfp 84 Text: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case	Original	PDF	TM1019 RTAX2000 footprint cqfp 280 RTAX1000S actel cqfp 84
56 pin edac connector Abstract: PCB footprint cqfp 132 Silicon Sculptor II ACTEL CCGA 624 mechanical Text: v2.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case	Original	PDF	TM1019 56 pin edac connector PCB footprint cqfp 132 Silicon Sculptor II ACTEL CCGA 624 mechanical
RTAX2000 Abstract: rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3 Text: v5.1 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg	Original	PDF	TM1019 RTAX2000 rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3
wd 969 ir Abstract: LVCMOS25 vhdl code for 4-bit shift register Text: QuickLogic PolarPro II Device Data Sheet •••••• Combining Low Power Programmable Fabric and Embedded SRAM • Quadrant-based segmentable clock networks Device Highlights  20 quad clock networks per device Low Power Programmable Logic  4 quad clock networks per quadrant	Original	PDF
sklansky adder verilog code Abstract: vhdl code for 8-bit brentkung adder dadda tree multiplier 8bit dadda tree multiplier 4 bit radix 2 modified booth multiplier code in vhdl 8-bit brentkung adder vhdl code Design of Wallace Tree Multiplier by Sklansky Adder 4 bit multiplication vhdl code using wallace tree vhdl code Wallace tree multiplier 16 bit carry lookahead subtractor vhdl Text: SmartGen Cores Reference Guide Hyperlinks in the SmartGen Cores Reference Guide PDF file are DISABLED. Please see the online help included with software to view the content with enabled links. Actel Corporation, Mountain View, CA 94043 2009 Actel Corporation. All rights reserved.	Original	PDF

Untitled Abstract: No abstract text available Text: Cyclone II Device Handbook, Volume 1 Preliminary Information 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com CII5V1-2.1 Copyright 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and	Original	PDF	896-Pin
EP2C8F256 package Abstract: S-2501-1 EP2C20F256 bga 896 TSMC 90nm sram Text: Section I. Cyclone II Device Family Data Sheet This section provides information for board layout designers to successfully layout their boards for Cyclone II devices. It contains the required PCB layout guidelines, device pin tables, and package specifications.	Original	PDF
bga 896 Abstract: AX1000 Text: Product Brief Axcelerator Family FPGAs Le adi n g- E dg e P e rfo r ma nc e • • • • 350+ MHz System Performance 500+ MHZ Internal Performance High-Performance Embedded FIFOs 622Mb/s LVDS Capable I/Os S pe ci fi c at i on s • • • • • Up to 2 Million Equivalent System Gates	Original	PDF	622Mb/s 339kbits JESD8-11) 5172160PB-3/6 bga 896 AX1000
Untitled Abstract: No abstract text available Text: v2 .1  Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates	Original	PDF	700Mb/s 295kbits
Untitled Abstract: No abstract text available Text: v2.6 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates	Original	PDF
Untitled Abstract: No abstract text available Text: QuickLogic PolarPro® II Device Data Sheet •••••• Combining Low Power Programmable Fabric and Embedded SRAM Device Highlights Low Power Programmable Logic • Up to 27 customizable building blocks CBBs (see Programmable Logic Architectural Overview	Original	PDF
RAM64K36 Abstract: wd19 RD23 RAM256X9 WD21 Text: A pp l i c a t i o n N o t e A C 1 7 7 Implementing Multi-Port Memories in Axcelerator Devices I n tro du ct i on This application note describes a user configurable VHDL wrapper for implementing dual-port and quad-port memory structures using a small number of programmable logic tiles	Original	PDF	128x36, 256x18, 512x9, RAM64K36 wd19 RD23 RAM256X9 WD21
RTAX1000SL Abstract: RTAX1000S RTAX1000S-SL RTAX250SL RTAX2000SL RTAX2000S RTAX250S RTAX4000S 56 pin edac connector Text: RTAX-S/SL RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment 3.3 V LVTTL Clamp Diode Hot Insertion / Cold Sparing 1 Yes 5V Tolerance Input Buffer Output Buffer No 1 Yes Enabled/Disabled Enabled/Disabled 3.3 V PCI	Original	PDF	JESD8-11) RTAX1000SL RTAX1000S RTAX1000S-SL RTAX250SL RTAX2000SL RTAX2000S RTAX250S RTAX4000S 56 pin edac connector
ACTEL CCGA 1152 mechanical Abstract: AX125 AX2000 CQ208 CQ256 CS180 FG256 PQ208 Trd16 Axcelerator Family FPGAs Text: v2.8 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates	Original	PDF
ACTEL CCGA 1152 mechanical Abstract: CS180 antifuse AX125 AX2000 CQ208 CQ256 FG256 PQ208 ACTEL CCGA 624 mechanical Text: v2.8 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates	Original	PDF

128X36 Search Results

128X36 Datasheets Context Search

verilog hdl code for matrix multiplication

OLED

1kx4

pin configuration of 7496 IC

asynchronous fifo vhdl

LGA 478 SOCKET PIN LAYOUT

Untitled

RTAX2000

RTAX2000

RTAX2000

56 pin edac connector

RTAX2000

wd 969 ir

sklansky adder verilog code

Untitled

EP2C8F256 package

bga 896

Untitled

Untitled

Untitled

RAM64K36

RTAX1000SL

ACTEL CCGA 1152 mechanical

ACTEL CCGA 1152 mechanical