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    transistor c331

    Abstract: c331 transistor C3318 C3317 C331 C3311 C331 datasheet CY7C331 20HC c331 equivalent
    Text: CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the


    Original     		PDF CY7C331 CY7C331 transistor c331 c331 transistor C3318 C3317 C331 C3311 C331 datasheet 20HC c331 equivalent

    San Ace 80

    Abstract: CY7C199-25SC 7C199-10 7C199-15 7C199-20 7C199-25 7C199-35 7C199-45 7C199-8 C199
    Text: fax id: 1030 1CY 7C19 9 CY7C199 32K x 8 Static RAM Features • High speed — 10 ns • Fast tDOE • CMOS for optimum speed/power • Low active power — 467 mW max, 12 ns “L” version • Low standby power — 0.275 mW (max, “L” version) • 2V data retention (“L” version only)


    Original     		PDF CY7C199 CY7C199 300-mil-wide San Ace 80 CY7C199-25SC 7C199-10 7C199-15 7C199-20 7C199-25 7C199-35 7C199-45 7C199-8 C199

    C3357

    Abstract: c3358 CERAMIC LEADLESS CHIP CARRIER diode c335 c3356 c3355 C335 CY7C335-66PC CY7C335 C3354
    Text: fax id: 6018 1CY 7C33 5 CY7C335 Universal Synchronous EPLD Features — 2-ns input set-up and 9-ns output register clock to output • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — 10-ns input register clock to state register clock


    Original     		PDF CY7C335 100-MHz 10-ns 28-pin, 300-mil C3357 c3358 CERAMIC LEADLESS CHIP CARRIER diode c335 c3356 c3355 C335 CY7C335-66PC CY7C335 C3354

    C344

    Abstract: 10HC 74HC 7C344 CY7C344 CY7C344B 7C344-25 TEA16
    Text: fax id: 6101 1CY 7C34 4B CY7C344 CY7C344B 32-Macrocell MAX EPLD Features sents the densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an


    Original     		PDF CY7C344 CY7C344B 32-Macrocell CY7C344 C344 10HC 74HC 7C344 CY7C344B 7C344-25 TEA16

    transistor c331

    Abstract: c331 transistor c331 c331 equivalent C3318 C3319 C3314 c3317 C3311 transistor c331 datasheet
    Text: fax id: 6016 1CY7C331 CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable


    Original     		PDF 1CY7C331 CY7C331 transistor c331 c331 transistor c331 c331 equivalent C3318 C3319 C3314 c3317 C3311 transistor c331 datasheet

    cy7c344b-25hmb

    Abstract: 10HC 74HC 7C344 C344 CY7C344 CY7C344B
    Text: fax id: 6101 1CY 7C34 4B CY7C344 CY7C344B 32-Macrocell MAX EPLD Features sents the densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an


    Original     		PDF CY7C344 CY7C344B 32-Macrocell CY7C344 cy7c344b-25hmb 10HC 74HC 7C344 C344 CY7C344B

    CY7C335

    Abstract: C3356 c3355 C335 C3358
    Text: CY7C335 Universal Synchronous EPLD — 2-ns input set-up and 9-ns output register clock to output Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — 10-ns input register clock to state register clock


    Original     		PDF CY7C335 100-MHz 10-ns 28-pin, 300-mil CY7C335 C3356 c3355 C335 C3358

    c3355

    Abstract: CY7C335 C335
    Text: CY7C335 Universal Synchronous EPLD Features — 2-ns input set-up and 9-ns output register clock to output • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — 10-ns input register clock to state register clock


    Original     		PDF CY7C335 100-MHz 10-ns 28-pin, 300-mil CY7C335 c3355 C335

    c331 equivalent

    Abstract: C3317 c331-12 c3311 192x pin diagram c331
    Text: CY7C331 Asynchronous Registered EPLD • Low power — 90 mA typical ICC quiescent Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the I/O


    Original     		PDF CY7C331 28-pin c331 equivalent C3317 c331-12 c3311 192x pin diagram c331

    CY7C428-65PC

    Abstract: CY7C419 CY7C421 CY7C425 CY7C429 CY7C433 IDT7200 IDT7201 IDT7202 IDT7203
    Text: fax id: 5404 CY7C419/21/25/29/33 -= C Y P R E S S 256/512 /1K /2K/4K x 9 Asynchronous FIFO Features • • • • • • • • • • • • • • • Asynchronous first-in first-out FIFO buffer memories 256 x 9 (CY7C419) 512 x 9 (CY7C421) 1 K x 9 (CY7C425)


    OCR Scan     		PDF CY7C419/21/25/29/33 CY7C419) CY7C421) CY7C425) CY7C429) CY7C433) 300-mil 600-mil IDT7200, IDT7201, CY7C428-65PC CY7C419 CY7C421 CY7C425 CY7C429 CY7C433 IDT7200 IDT7201 IDT7202 IDT7203

    CY7C

    Abstract: 330 j65
    Text: ~ g r ^ = » » » “ 'V ' a - ^ ; r n t Æ e i0 _ C Y 7 C 4 1 9 / 2 1 / 2 5 / 2 9 / 3 3 256/512/1K/2K/4K x 9 Asynchronous FIFO Features • Asynchronous first-in first-out FIFO buffer memories • 256 x 9 (CY7C419) • 512 x 9 (CY7C421 )


    OCR Scan     		PDF 256/512/1K/2K/4K CY7C419) CY7C421 CY7C425) CY7C429) CY7C433) 300-mil 600-mil IDT7200, IDT7201, CY7C 330 j65

    Untitled

    Abstract: No abstract text available
    Text: fax id: 6018 CY7C335 3F CYPRESS Universal Synchronous EPLD Features — 2-ns in p u t se t-u p and 9-ns o u tp u t re g is te r c lo c k to o u tp u t • 100-MHz o u tp u t re g iste re d o p e ra tio n • Tw elve I/O m a c ro c e lls , each h a vin g :


    OCR Scan     		PDF CY7C335 100-MHz 10-ns 28-pin, 300-m CY7C335

    CY7C

    Abstract: c42010
    Text: fax id: 5404 •■■■■■■'■jH/m'r. a S S K , : 'S^i,„*$ & :*■ CY7C419/21/25/29/33 _ . " T jg i? 256/512 /1K /2K/4K x 9 Asynchronous FIFO Features Asynchronous first-in first-out FIFO buffer memories 256 x 9 (CY7C419) 512 x 9 (CY7C421)


    OCR Scan     		PDF CY7C419/21/25/29/33 CY7C419) CY7C421) CY7C425) CY7C429) CY7C433) 300-mil 600-mil IDT7200, IDT7201, CY7C c42010

    CY7C

    Abstract: 7C433 42930 7c429
    Text: fax id: 5404 § 1 p ^ y p p p c jc ; CY7C419/21/25/29/33 256/512 /1K /2K/4K x 9 Asynchronous FIFO Features • • • • • • • • • • • • • • • Asynchronous first-in first-out FIFO buffer memories 256 x 9 (CY7C419) 512 x 9 (CY7C421)


    OCR Scan     		PDF CY7C419/21/25/29/33 CY7C419) CY7C421) CY7C425) CY7C429) CY7C433) 300-mil 600-mil IDT7200, IDT7201, CY7C 7C433 42930 7c429

    TCO - 909

    Abstract: TCO - 909 F 10 MHz CERAMIC LEADLESS CHIP CARRIER CY7C335 CY7C335-50
    Text: fax id: 6018 CY7C335 Universal Synchronous EPLD Features — 2-ns input set-up and 9-ns output register clock to output 100-MHz output registered operation Twelve I/O macrocells, each having: — 10-ns input register clock to state register clock — Registered, three-state I/O pins


    OCR Scan     		PDF 100-MHz TCO - 909 TCO - 909 F 10 MHz CERAMIC LEADLESS CHIP CARRIER CY7C335 CY7C335-50

    7c331

    Abstract: c33115
    Text: 7C331:1/92 Revision: December 1992 fax id: 6016 CY7C331 V CYPRESS Asynchronous Registered EPLD • Low power Features — 90 mA typical lcc quiescent • Twelve I/O macro cel Is each having: — One state flip-flop with an XOR sum-of-products input — 180 mA lcc maximum


    OCR Scan     		PDF 7C331 28-pights. CY7C331 28-Lead 300-Mil) MIL-STD-1835 15Config c33115

    CY7C425

    Abstract: CY7C419 CY7C421 CY7C429 CY7C433 IDT7200 IDT7201 IDT7202 IDT7203 IDT7204
    Text: fax id: 5404 CY7C419/21/25/29/33 -= C Y P R E S S 256/512 /1K /2K/4K x 9 Asynchronous FIFO Features • • • • • • • • • • • • • • • Asynchronous first-in first-out FIFO buffer memories 256 x 9 (CY7C419) 512 x 9 (CY7C421) 1 K x 9 (CY7C425)


    OCR Scan     		PDF CY7C419/21/25/29/33 CY7C419) CY7C421) CY7C425) CY7C429) CY7C433) 300-mil 600-mil IDT7200, IDT7201, CY7C425 CY7C419 CY7C421 CY7C429 CY7C433 IDT7200 IDT7201 IDT7202 IDT7203 IDT7204